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| PIC18C601/801 High-Performance ROM-less Microcontrollers with External Memory Bus High Performance RISC CPU: * C compiler optimized architecture instruction set * Linear program memory addressing up to 2 Mbytes * Linear data memory addressing to 4 Kbytes External Program Memory On-Chip Device Maximum Addressing (bytes) 256K 2M Maximum Single Word Instructions 128K 1M On-Chip RAM (bytes) Advanced Analog Features: * 10-bit Analog-to-Digital Converter module (A/D) with: - Fast sampling rate - Conversion available during SLEEP - DNL = 1 LSb, INL = 1 LSb - Up to 12 channels available * Programmable Low Voltage Detection (LVD) module - Supports interrupt on Low Voltage Detection PIC18C601 PIC18C801 1.5K 1.5K Special Microcontroller Features: * Power-on Reset (POR), Power-up Timer (PWRT), and Oscillator Start-up Timer (OST) * Watchdog Timer (WDT) with its own on-chip RC oscillator * On-chip Boot RAM for boot loader application * 8-bit or 16-bit external memory interface modes * Up to two software programmable chip select signals (CS1 and CS2) * One programmable chip I/O select signal (CSIO) for memory mapped I/O expansion * Power saving SLEEP mode * Different oscillator options, including: - 4X Phase Lock Loop (of primary oscillator) - Secondary Oscillator (32 kHz) clock input * Up to 160 ns instruction cycle: - DC - 25 MHz clock input - 4 MHz - 6 MHz clock input with PLL active * 16-bit wide instructions, 8-bit wide data path * Priority levels for interrupts * 8 x 8 Single Cycle Hardware Multiplier Peripheral Features: * * * * * * * * * High current sink/source 25 mA/25 mA Up to 47 I/O pins with individual direction control Three external interrupt pins Timer0 module: 8-bit/16-bit timer/counter with 8-bit programmable prescaler Timer1 module: 16-bit timer/counter (time-base for CCP) Timer2 module: 8-bit timer/counter with 8-bit period register Timer3 module: 16-bit timer/counter Secondary oscillator clock option - Timer1/Timer3 Two Capture/Compare/PWM (CCP) modules CCP pins can be configured as: - Capture input: 16-bit, max. resolution 10 ns - Compare is 16-bit, max. resolution 160 ns (TCY) - PWM output: PWM resolution is 1- to 10-bit Max. PWM freq. @: 8-bit resolution = 99 kHz 10-bit resolution = 24.4 kHz Master Synchronous Serial Port (MSSP) with two modes of operation: - 3-wire SPITM (Supports all 4 SPI modes) - I2CTM Master and Slave mode Addressable USART module: Supports Interrupt on Address bit CMOS Technology: * * * * * Low power, high speed CMOS technology Fully static design Wide operating voltage range (2.0V to 5.5V) Industrial and Extended temperature ranges Low power consumption * * 2001 Microchip Technology Inc. Advance Information DS39541A-page 1 PIC18C601/801 Pin Diagrams 64-Pin TQFP RE2/AD10 RE3/AD11 RE4/AD12 RE5/AD13 RE6/AD14 RE7/AD15 RD0/AD0 VDD VSS RD1/AD1 RD2/AD2 RD3/AD3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RE1/AD9 RE0/AD8 RG0/ALE RG1/OE RG2/WRL RG3/WRH MCLR/VPP RG4/BA0 VSS VDD RF7/UB RF6/LB RF5/CS1 RF4/A16 RF3/CSIO RF2/AN7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RD4/AD4 RD5/AD5 RD6/AD6 RD7/AD7 48 47 46 45 44 43 42 RB0/INT0 RB1/INT1 RB2/INT2 RB3/CCP2 RB4 RB5 RB6 VSS OSC2/CLKO OSC1/CLKI VDD RB7 RC5/SDO RC4/SDI/SDA RC3/SCK/SCL RC2/CCP1 PIC18C601 41 40 39 38 37 36 35 34 33 AVSS RA3/AN3/VREF+ DS39541A-page 2 Advance Information RC0/T1OSO/T13CKI RC6/TX/CK RC7/RX/DT RA0/AN0 VSS RF0/AN5 AVDD VDD RA5/SS/AN4/LVDIN RA2/AN2/VREF- RA4/T0CKI RC1/T1OSI RF1/AN6 RA1/AN1 2001 Microchip Technology Inc. PIC18C601/801 Pin Diagrams (Cont.'d) 68-Pin PLCC RE2/AD10 RE3/AD11 RE4/AD12 RE5/AD13 RE6/AD14 RE7/AD15 RD0/AD0 VDD NC VSS RD1/AD1 RD2/AD2 RD3/AD3 RD4/AD4 RD5/AD5 RD6/AD6 RD7/AD7 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 RE1/AD9 RE0/AD8 RG0/ALE RG1/OE RG2/WRL RG3/WRH MCLR/VPP RG4/BA0 NC VSS VDD RF7/UB RF6/LB RF5/CS1 RF4/A16 RF3/CSIO RF2/AN7 PIC18C601 RB0/INT0 RB1/INT1 RB2/INT2 RB3/CCP2 RB4 RB5 RB6 VSS NC OSC2/CLKO OSC1/CLKI VDD RB7 RC5/SDO RC4/SDI/SDA RC3/SCK/SCL RC2/CCP1 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 RF1/AN6 RF0/AN5 AVDD AVSS RA3/AN3/VREF+ RA2/AN2/VREFRA1/AN1 RA0/AN0 NC VSS 2001 Microchip Technology Inc. Advance Information VDD RA5/SS/AN4/LVDIN RA4/T0CKI RC1/T1OSI RC0/T1OSO/T13CKI RC6/TX/CK RC7/RX/DT DS39541A-page 3 PIC18C601/801 Pin Diagrams (Cont.'d) 80-Pin TQFP RH1/A17 RH0/A16 RE2/AD10 RE3/AD11 RE4/AD12 RE5/AD13 RE6/AD14 RE7/AD15 RD0/AD0 VDD VSS RD1/AD1 RD2/AD2 RD3/AD3 RD4/AD4 RD5/AD5 RD6/AD6 RD7/AD7 RJ0/D7 RJ1/D6 60 59 58 57 56 55 54 53 52 51 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 RH2/A18 RH3/A19 RE1/AD9 RE0/AD8 RG0/ALE RG1/OE RG2/WRL RG3/WRH MCLR/VPP RG4/BA0 VSS VDD RF7/UB RF6/LB RF5/CS1 RF4/CS2 RF3/CSIO RF2/AN7 RH4/AN8 RH5/AN9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 RJ5/D5 RJ4/D4 RB0/INT0 RB1/INT1 RB2/INT2 RB3/CCP2 RB4 RB5 RB6 VSS OSC2/CLKO OSC1/CLKI VDD RB7 RC5/SDO RC4/SDI/SDA RC3/SCK/SCL RC2/CCP1 RJ3/D3 RJ2/D2 PIC18C801 49 48 47 46 45 44 43 42 41 RF1/AN6 RF0/AN5 AVDD AVSS RA3/AN3/VREF+ RA2/AN2/VREF- RA5/SS/AN4/LVDIN RA4/T0CKI RC1/T1OSI DS39541A-page 4 Advance Information RC0/T1OSO/T13CKI RC6/TX/CK RC7/RX/DT RH6/AN10 RH7/AN11 RA1/AN1 RA0/AN0 VSS RJ0/D0 RJ1/D1 2001 Microchip Technology Inc. VDD PIC18C601/801 Pin Diagrams (Cont.'d) 84-Pin PLCC RH1/A17 RH0/A16 RE2/AD10 RE3/AD11 RE4/AD12 RE5/AD13 RE6/AD14 RE7/AD15 RD0/AD0 VDD NC VSS RD1/AD1 RD2/AD2 RD3/AD3 RD4/AD4 RD5/AD5 RD6/AD6 RD7/AD7 RJ7/D7 RJ6/D6 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 RH2/A18 RH3/A19 RE1/AD9 RE0/AD8 RG0/ALE RG1/OE RG2/WRL RG3/WRH MCLR/VPP RG4/BA0 NC VSS VDD RF7/UB RF6/LB RF5/CS1 RF4/CS2 RF3/CSIO RF2/AN7 RH4/AN8 RH5/AN9 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PIC18C801 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 RJ5/D5 RJ4/D4 RB0/INT0 RB1/INT1 RB2/INT2 RB3/CCP2 RB4 RB5 RB6 VSS NC OSC2/CLKO OSC1/CLKI VDD RB7 RC5/SDO RC4/SDI/SDA RC3/SCK/SCL RC2/CCP1 RJ3/D3 RJ2/D2 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 2001 Microchip Technology Inc. RH6/AN10 RH7/AN11 RF1/AN6 RF0/AN5 AVDD AVSS RA3/AN3/VREF+ RA2/AN2/VREFRA1/AN1 RA0/AN0 NC VSS VDD RA5/SS/AN4/LVDIN RA4/T0CKI RC1/T1OSI RC0/T1OSO/T13CKI RC6/TX/CK RC7/RX/DT RJ0/D0 RJ1/D1 Advance Information DS39541A-page 5 PIC18C601/801 Table of Contents 1.0 Device Overview.................................................................................................................................................. 9 2.0 Oscillator Configurations.................................................................................................................................... 21 3.0 RESET............................................................................................................................................................... 29 4.0 Memory Organization ........................................................................................................................................ 39 5.0 External Memory Interface................................................................................................................................. 63 6.0 Table Reads/Table Writes ................................................................................................................................. 73 7.0 8 X 8 Hardware Multiplier .................................................................................................................................. 85 8.0 Interrupts............................................................................................................................................................ 89 9.0 I/O Ports........................................................................................................................................................... 103 10.0 Timer0 Module................................................................................................................................................. 127 11.0 Timer1 Module................................................................................................................................................. 130 12.0 Timer2 Module................................................................................................................................................. 135 13.0 Timer3 Module................................................................................................................................................. 137 14.0 Capture/Compare/PWM (CCP) Modules......................................................................................................... 141 15.0 Master Synchronous Serial Port (MSSP) Module............................................................................................ 149 16.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART) ..................................... 177 17.0 10-bit Analog-to-Digital Converter (A/D) Module ............................................................................................. 193 18.0 Low Voltage Detect.......................................................................................................................................... 203 19.0 Special Features of the CPU ........................................................................................................................... 207 20.0 Instruction Set Summary ................................................................................................................................. 215 21.0 Development Support ...................................................................................................................................... 259 22.0 Electrical Characteristics ................................................................................................................................. 265 23.0 DC and AC Characteristics Graphs and Tables .............................................................................................. 295 24.0 Packaging Information ..................................................................................................................................... 297 Appendix A: Data Sheet Revision History.................................................................................................................. 303 Appendix B: Device Differences ................................................................................................................................ 303 Appendix C: Device Migrations .................................................................................................................................. 304 Appendix D: Migrating from other PICmicro Devices ................................................................................................. 304 Appendix E: Development Tool Version Requirements ............................................................................................. 305 Index ........................................................................................................................................................................... 307 On-Line Support .......................................................................................................................................................... 315 Reader Response ....................................................................................................................................................... 316 Product Identification System...................................................................................................................................... 317 DS39541A-page 6 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) * The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. 2001 Microchip Technology Inc. Advance Information DS39541A-page 7 PIC18C601/801 NOTES: DS39541A-page 8 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 1.0 DEVICE OVERVIEW An overview of features is shown in Table 1-1. Device block diagrams are provided in Figure 1-1 for the 64/68-pin configuration, and Figure 1-2 for the 80/ 84-pin configuration. The pinouts for both packages are listed in Table 1-2. This document contains device specific information for the following two devices: 1. 2. PIC18C601 PIC18C801 The PIC18C601 is available in 64-pin TQFP and 68-pin PLCC packages. The PIC18C801 is available in 80-pin TQFP and 84-pin PLCC packages. TABLE 1-1: DEVICE FEATURES Features PIC18C601 DC - 25 MHz Bytes Max. # of Single Word Instructions 256K 128K 1536 15 Ports A - G 4 2 MSSP, Addressable USART 8 input channels POR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST) Yes Yes No Yes CS1 Yes 75 Instructions 64-pin TQFP 68-pin PLCC PIC18C801 DC - 25 MHz 2M 1M 1536 15 Ports A - H, J 4 2 MSSP, Addressable USART 12 input channels POR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST) Yes Yes Yes Yes CS1, CS2 Yes 75 Instructions 80-pin TQFP 84-pin PLCC Operating Frequency External Program Memory Data Memory (Bytes) Interrupt Sources I/O Ports Timers Capture/Compare/PWM modules Serial Communications 10-bit Analog-to-Digital Module RESETS (and Delays) Programmable Low Voltage Detect 8-bit External Memory Interface 8-bit De-multiplexed External Memory Interface 16-bit External Memory Interfaces On-chip Chip Select Signals On-chip I/O Chip Select Signal Instruction Set Packages 2001 Microchip Technology Inc. Advance Information DS39541A-page 9 PIC18C601/801 FIGURE 1-1: AD7:AD0 PIC18C601 BLOCK DIAGRAM Data Bus<8> PORTA RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS/LVDIN PORTB RB0/INT0 RB1/INT1 RB2/INT2 RB3/CCP2 RB4 RB5 RB6 RB7 PORTC 16 Table Latch Decode inc/dec logic Table Pointer<21> Data Latch 21 21 5 inc/dec logic 8 8 Data RAM 1 Kbyte Address Latch 20 System Bus Interface 21 Address Latch Program Memory (up to 256 Kbytes) Data Latch PCLATU PCLATH PCU PCH PCL Program Counter 12 Address<12> 4 BSR 12 FSR0 FSR1 FSR2 4 Bank0, F 31 Level Stack 12 8 ROM Latch IR RC0/T1OSO/T13CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX1/CK1 RC7/RX1/DT1 8 PORTD A16, AD15:AD8 Instruction Decode & Control OSC2/CLKO OSC1/CLKI Timing Generation 3 Power-up Timer Oscillator Start-upTimer Power-on Reset Watchdog Timer Low Voltage Detect PRODH PRODL 8 x 8 Multiply 8 PORTE BITOP 8 WREG 8 8 ALU<8> PORTF 8 8 RD7:RD0/AD7:AD0 T1OSI T1OSO RE7:RE0/AD15:AD8 MCLR VDD, VSS RF0/AN5 RF1/AN6 RF2/AN7 RF3/CSIO RF4/A16 RF5/CS1 RF6/LB RF7/UB PORTG RG0/ALE RG1/OE RG2/WRL RG3/WRH RG4/BA0 Timer0 Timer1 Timer2 Timer3 CCP1 CCP2 Synchronous Serial Port USART1 10-bit A/D DS39541A-page 10 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 FIGURE 1-2: AD7:AD0 PIC18C801 BLOCK DIAGRAM Data Bus<8> PORTA RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS/LVDIN PORTB RB0/INT0 RB1/INT1 RB2/INT2 RB3/CCP2 RB4 RB5 RB6 RB7 PORTC RC0/T1OSO/T13CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX1/CK1 RC7/RX1/DT1 PORTD 8 RD7:RD0/AD7:AD0 PRODH PRODL 3 Power-up Timer Oscillator Start-upTimer Power-on Reset Watchdog Timer Low Voltage Detect 8 x 8 Multiply 8 BITOP 8 WREG 8 8 ALU<8> 8 RE7:RE0/AD15:AD8 8 PORTF RF0/AN5 RF1/AN6 RF2/AN7 RF3/CSIO RF4/CS2 RF5/CS1 RF6/LB RF7/UB PORTG RG0/ALE RG1/OE RG2/WRL RG3/WRH RG4/BA0 PORTE TablePointer<21> Data Latch 5 21 21 inc/dec logic 8 8 Data RAM 1 Kbyte Address Latch 20 System Bus Interface 21 Address Latch Program Memory (up to 2 Mbytes) PCLATU PCLATH PCU PCH PCL Program Counter 12 Address<12> 4 BSR 12 FSR0 FSR1 FSR2 inc/dec logic 4 Bank0,F 31 Level Stack Data Latch 12 16 Decode Table Latch 8 ROM Latch IR A19:A16, AD15:AD0 Instruction Decode & Control OSC2/CLKO OSC1/CLKI Timing Generation T1OSI T1OSO MCLR VDD, VSS Timer0 Timer1 Timer2 Timer3 PORTH RH3:RH0/A19:A16 RH4/AN8 RH5/AN9 RH6/AN10 RH7/AN11 CCP1 CCP2 Synchronous Serial Port USART1 PORTJ RJ7:RJ0/D7:D0 10-bit A/D 2001 Microchip Technology Inc. Advance Information DS39541A-page 11 PIC18C601/801 TABLE 1-2: PINOUT I/O DESCRIPTIONS Pin Number Pin Name PIC18C601 TQFP MCLR/VPP MCLR VPP NC OSC1/CLKI OSC1 7 PLCC 16 PIC18C801 TQFP 9 PLCC 20 I P ST Master clear (RESET) input. This pin is an active low RESET to the device. Programming voltage input. These pins should be left unconnected. Oscillator crystal input or external clock source input. ST buffer when in RC mode. Otherwise CMOS. External clock source input. Always associated with pin function OSC1 (see OSC1/CLKI, OSC2/CLKO pins). Pin Type Buffer Type Description -- 39 1, 18, 35, 52 50 -- 49 1, 22, 43, 64 62 -- -- I CMOS/ST CLKI I CMOS OSC2/CLKO OSC2 40 51 50 63 O -- CLKO O -- Legend: TTL ST I P = = = = TTL compatible input Schmitt Trigger input with CMOS levels Input Power CMOS Analog O OD = = = = Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. CMOS compatible input or output Analog input Output Open Drain (no P diode to VDD) DS39541A-page 12 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18C601 TQFP RA0/AN0 RA0 AN0 RA1/AN1 RA1 AN1 RA2/AN2/VREFRA2 AN2 VREFRA3/AN3/VREF+ RA3 AN3 VREF+ RA4/T0CKI RA4 24 PLCC 34 PIC18C801 TQFP 30 PLCC 42 I/O I 23 33 29 41 I/O I 22 32 28 40 I/O I I 21 31 27 39 I/O I I 28 39 34 47 I/O I I/O I I I ST/OD ST Digital I/O - Open drain when configured as output. Timer0 external clock input. TTL Analog Analog Digital I/O. Analog input 3. A/D reference voltage (High) input. TTL Analog Analog Digital I/O. Analog input 2. A/D reference voltage (Low) input. TTL Analog Digital I/O. Analog input 1. TTL Analog Digital I/O. Analog input 0. Pin Type Buffer Type Description PORTA is a bi-directional I/O port. T0CKI RA5/AN4/SS/LVDIN 27 38 33 46 RA5 AN4 SS LVDIN Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power TTL Digital I/O. Analog Analog input 4. ST SPI slave select input. Analog Low voltage detect input. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open Drain (no P diode to VDD) 2001 Microchip Technology Inc. Advance Information DS39541A-page 13 PIC18C601/801 TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18C601 TQFP PLCC PIC18C801 TQFP PLCC Pin Type Buffer Type Description PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0 RB0 INT0 RB1/INT1 RB1 INT1 RB2/INT2 RB2 INT2 RB3/CCP2 RB3 CCP2 RB4 RB5 RB6 RB7 Legend: TTL ST I P = = = = 48 60 58 72 I/O I 47 59 57 71 I/O I 46 58 56 70 I/O I 45 57 55 69 Digital I/O. Capture2 input, Compare2 output, PWM2 output. I/O TTL Digital I/O, Interrupt-on-change pin. I/O TTL Digital I/O, Interrupt-on-change pin. I/O TTL Digital I/O, Interrupt-on-change pin. I ST ICSP programming clock. I/O TTL Digital I/O, Interrupt-on-change pin. I/O ST ICSP programming data. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open Drain (no P diode to VDD) I/O I/O TTL ST TTL ST Digital I/O. External interrupt 2. TTL ST Digital I/O. External interrupt 1. TTL ST Digital I/O. External interrupt 0. 44 43 42 37 56 55 54 48 54 53 52 47 68 67 66 60 TTL compatible input Schmitt Trigger input with CMOS levels Input Power DS39541A-page 14 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18C601 TQFP RC0/T1OSO/T13CKI RC0 T1OSO T13CKI RC1/T1OSI RC1 T1OSI RC2/CCP1 RC2 CCP1 RC3/SCK/SCL RC3 SCK SCL RC4/SDI/SDA RC4 SDI SDA RC5/SDO RC5 SDO RC6/TX/CK RC6 TX CK RC7/RX/DT RC7 RX DT Legend: TTL ST I P 35 46 45 58 I/O I I/O 36 47 46 59 I/O O 31 42 37 50 I/O O I/O 32 43 38 51 I/O I I/O = = = = TTL compatible input Schmitt Trigger input with CMOS levels Input Power ST Digital I/O. ST USART asynchronous receive. ST USART synchronous data. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open Drain (no P diode to VDD) ST -- ST Digital I/O. USART asynchronous transmit. USART synchronous clock. ST ST ST ST Digital I/O. SPI data in. I2C data I/O. Digital I/O. SPI data out. 30 PLCC 41 PIC18C801 TQFP 36 PLCC 49 I/O O I 29 40 35 48 I/O I 33 44 43 56 I/O I/O 34 45 44 57 I/O I/O I/O ST ST ST Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2C mode. ST ST Digital I/O. Capture1 input/Compare1 output/PWM1 output. ST CMOS Digital I/O. Timer1 oscillator input. ST Pin Type Buffer Type Description PORTC is a bi-directional I/O port. Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input. -- ST -- 2001 Microchip Technology Inc. Advance Information DS39541A-page 15 PIC18C601/801 TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18C601 TQFP PLCC PIC18C801 TQFP PLCC Pin Type Buffer Type Description PORTD is a bi-directional I/O port. These pins have TTL input buffers when external memory is enabled. RD0/AD0 RD0 AD0 RD1/AD1 RD1 AD1 RD2/AD2 RD2 AD2 RD3/AD3 RD3 AD3 RD4/AD4 RD4 AD4 RD5/AD5 RD5 AD5 RD6/AD6 RD6 AD6 RD7/AD7 RD7 AD7 Legend: TTL ST I P 58 3 72 3 I/O I/O 55 67 69 83 I/O I/O 54 66 68 82 I/O I/O 53 65 67 81 I/O I/O 52 64 66 80 I/O I/O 51 63 65 79 I/O I/O 50 62 64 78 I/O I/O 49 61 63 77 I/O I/O = = = = TTL compatible input Schmitt Trigger input with CMOS levels Input Power ST Digital I/O. TTL External memory address/data 7. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open Drain (no P diode to VDD) ST TTL Digital I/O. External memory address/data 6. ST TTL Digital I/O. External memory address/data 5. ST TTL Digital I/O. External memory address/data 4. ST TTL Digital I/O. External memory address/data 3. ST TTL Digital I/O. External memory address/data 2. ST TTL Digital I/O. External memory address/data 1. ST TTL Digital I/O. External memory address/data 0. DS39541A-page 16 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18C601 TQFP RE0/AD8 RE0 AD8 RE1/AD9 RE1 AD9 RE2/AD10 RE2 AD10 RE3/AD11 RE3 AD11 RE4/AD12 RE4 AD12 RE5/AD13 RE5 AD13 RE6/AD14 RE6 AD14 RE7/AD15 RE7 AD15 Legend: TTL ST I P 2 PLCC 11 PIC18C801 TQFP 4 PLCC 15 I/O I/O 1 10 3 14 I/O I/O 64 9 78 9 I/O I/O 63 8 77 8 I/O I/O 62 7 76 7 I/O I/O 61 6 75 6 I/O I/O 60 5 74 5 I/O I/O 59 4 73 4 I/O I/O = = = = TTL compatible input Schmitt Trigger input with CMOS levels Input Power ST Digital I/O. ST External memory address/data 15. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open Drain (no P diode to VDD) ST TTL Digital I/O. External memory address/data 14. ST TTL Digital I/O. External memory address/data 13. ST TTL Digital I/O. External memory address/data 12. ST TTL Digital I/O. External memory address/data 11. ST TTL Digital I/O. External memory address/data 10. ST TTL Digital I/O. External memory address/data 9. ST TTL Digital I/O. External memory address/data 8. Pin Type Buffer Type Description PORTE is a bi-directional I/O port. 2001 Microchip Technology Inc. Advance Information DS39541A-page 17 PIC18C601/801 TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18C601 TQFP RF0/AN5 RF0 AN5 RF1/AN6 RF1 AN6 RF2/AN7 RF2 AN7 RF3/CSIO RF3 CSIO RF4/A16 RF4/CS2 RF4 A16 CS2 RF5/CS1 RF5 CS1 RF6/LB RF6 LB RF7/UB RF7 UB Legend: TTL ST I P = = = = 18 PLCC 28 PIC18C801 TQFP 24 PLCC 36 I/O I 17 27 23 35 I/O I 16 26 18 30 I/O I 15 25 17 29 I/O I/O 14 24 ST ST Digital I/O. System bus chip select I/O. ST Analog Digital I/O. Analog input 7. ST Analog Digital I/O. Analog input 6. ST Analog Digital I/O. Analog input 5. Pin Type Buffer Type Description PORTF is a bi-directional I/O port. -- 16 -- 28 I/O I/O O ST TTL TTL ST TTL ST TTL Digital I/O. External memory address 16. Chip select 2. Digital I/O. Chip select 1. Digital I/O. Low byte select signal for external memory interface. -- -- 13 23 15 27 I/O O 12 22 14 26 I/O O 11 21 13 25 I/O O ST TTL CMOS Analog O OD = = = = Digital I/O. High byte select signal for external memory interface. CMOS compatible input or output Analog input Output Open Drain (no P diode to VDD) TTL compatible input Schmitt Trigger input with CMOS levels Input Power DS39541A-page 18 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18C601 TQFP RG0/ALE RG0 ALE RG1/OE RG1 OE RG2/WRL RG2 WRL RG3/WRH RG3 WRH RG4/BA0 RG4 BA0 RH0/A16 RH0 A16 RH1/A17 RH1 A17 RH2/A18 RH2 A18 RH3/A19 RH3 A19 RH4/AN8 RH4 AN8 RH5/AN9 RH5 AN9 RH6/AN10 RH6 AN10 RH7/AN11 RH7 AN11 Legend: TTL ST I P 3 PLCC 12 PIC18C801 TQFP 5 PLCC 16 I/O O 4 13 6 17 I/O O 5 14 7 18 I/O O 6 15 8 19 I/O O 8 17 10 21 I/O O ST TTL Digital I/O. System bus byte address 0. PORTH is a bi-directional I/O port. Digital I/O. External memory address 16. Digital I/O. External memory address 17. Digital I/O. External memory address 18. Digital I/O. External memory address 19. Digital I/O. Analog input 8. Digital I/O. Analog input 9. Digital I/O. Analog input 10. ST TTL Digital I/O. Write High control. ST TTL Digital I/O. Write Low control. ST TTL Digital I/O. Output Enable. ST TTL Digital I/O. Address Latch Enable. Pin Type Buffer Type Description PORTG is a bi-directional I/O port. -- -- 79 10 I/O O ST TTL ST -- -- 80 11 I/O O -- ST -- -- 1 12 I/O O -- ST -- -- 2 13 I/O O -- ST Analog ST Analog ST Analog -- -- 19 31 I/O I -- -- 20 32 I/O I -- -- 21 33 I/O I -- -- 22 34 I/O I ST Digital I/O. Analog Analog input 11. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open Drain (no P diode to VDD) = = = = TTL compatible input Schmitt Trigger input with CMOS levels Input Power 2001 Microchip Technology Inc. Advance Information DS39541A-page 19 PIC18C601/801 TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18C601 TQFP RJ0/D0 RJ0 D0 RJ1/D1 RJ1 D1 RJ2/D2 RJ2 D2 RJ3/D3 RJ3 D3 RJ4/D4 RJ4 D4 RJ5/D5 RJ5 D5 RJ6/D6 RJ6 D6 RJ7/D7 RJ7 D7 VSS VDD AVSS AVDD Legend: TTL ST I P = = = = PLCC PIC18C801 TQFP 39 PLCC 52 I/O I/O ST TTL ST TTL ST TTL ST TTL ST TTL ST TTL ST TTL ST TTL Digital I/O. System bus data bit 0. Digital I/O. System bus data bit 1. Digital I/O. System bus data bit 2. Digital I/O. System bus data bit 3. Digital I/O. System bus data bit 4. Digital I/O. System bus data bit 5. Digital I/O. System bus data bit 6. Digital I/O. System bus data bit 7. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins. Ground reference for analog modules. Positive supply for analog modules. CMOS compatible input or output Analog input Output Open Drain (no P diode to VDD) Pin Type Buffer Type Description PORTJ is a bi-directional I/O port. -- -- -- -- 40 53 I/O I/O -- -- 41 54 I/O I/O -- -- 42 55 I/O I/O -- -- 59 73 I/O I/O -- -- 60 74 I/O I/O -- -- 61 75 I/O I/O -- -- 62 76 I/O I/O P P P P CMOS Analog O OD 9, 25, 41, 56 10,26, 38, 57 20 19 19, 36, 53, 68 2, 20, 37, 49 30 29 11,31, 51, 70 12,32, 48, 71 26 25 23, 44, 65, 84 2, 24, 45, 61 38 37 -- -- -- -- = = = = TTL compatible input Schmitt Trigger input with CMOS levels Input Power DS39541A-page 20 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 2.0 2.1 OSCILLATOR CONFIGURATIONS Oscillator Types FIGURE 2-1: CRYSTAL/CERAMIC RESONATOR OPERATION (HS OR LP OSC CONFIGURATION) OSC1 To Internal Logic SLEEP PIC18C601/801 PIC18C601/801 can be operated in one of four oscillator modes, programmable by configuration bits FOSC1:FOSC0 in CONFIG1H register: 1. 2. 3. 4. LP HS RC EC Low Power Crystal High Speed Crystal/Resonator External Resistor/Capacitor External Clock C1(1) XTAL RS(2) C2(1) OSC2 RF(3) 2.2 Crystal Oscillator/Ceramic Resonators Note 1: See Table 2-1 and Table 2-2 for recommended values of C1 and C2. 2: A series resistor (RS) may be required for AT strip cut crystals. 3: RF varies with the crystal chosen. In LP or HS oscillator modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation. Figure 2-1 shows the pin connections. An external clock source may also be connected to the OSC1 pin, as shown in Figure 2-3 and Figure 2-4. PIC18C601/801 oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a frequency out of the crystal manufacturer's specifications. 2001 Microchip Technology Inc. Advance Information DS39541A-page 21 PIC18C601/801 TABLE 2-1: CERAMIC RESONATORS Ranges Tested: Mode HS Freq. OSC1 OSC2 Note 1: Recommended values of C1 and C2 are identical to the ranges tested (Table 2-1). 2: Higher capacitance increases the stability of the oscillator, but also increases the start-up time. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: Rs may be required in HS mode to avoid overdriving crystals with low drive level specification. 8.0 MHz 10 - 68 pF 10 - 68 pF 16.0 MHz 10 - 22 pF 10 - 22 pF 20.0 MHz TBD TBD 25.0 MHz TBD TBD HS+PLL 4.0 MHz TBD TBD These values are for design guidance only. See notes on this page. Resonators Used: 4.0 MHz Murata Erie CSA4.00MG 0.5% 8.0 MHz Murata Erie CSA8.00MT 0.5% 16.0 MHz Murata Erie CSA16.00MX 0.5% All resonators used did not have built-in capacitors. 2.3 RC Oscillator TABLE 2-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Crystal Freq. 32.0 kHz 200 kHz 4.0 MHz 8.0 MHz 20.0 MHz 25.0 MHz Cap. Range C1 33 pF 15 pF 15 pF 15-33 pF 15-33 pF TBD 15 pF Cap. Range C2 33 pF 15 pF 15 pF 15-33 pF 15-33 pF TBD 15 pF Osc Type LP HS For timing insensitive applications, the "RC" oscillator mode offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 2-2 shows how the RC combination is connected. In the RC oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. HS+PLL 4.0 MHz FIGURE 2-2: VDD REXT RC OSCILLATOR MODE These values are for design guidance only. See notes on this page. Crystals Used 32.0 kHz 200 kHz 1.0 MHz 4.0 MHz 8.0 MHz Epson C-001R32.768K-A STD XTL 200.000kHz ECS ECS-10-13-1 ECS ECS-40-20-1 EPSON CA-301 8.000M-C 20 PPM 20 PPM 50 PPM 50 PPM 30 PPM 30 PPM CEXT VSS OSC1 Internal Clock PIC18C601/801 20.0 MHz EPSON CA-301 20.000M-C FOSC/4 or I/O Recommended values: OSC2/CLKO 3 k REXT 100 k CEXT > 20pF DS39541A-page 22 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 2.4 External Clock Input 2.5 HS4 (PLL) The EC oscillator mode requires an external clock source to be connected to the OSC1 pin. The feedback device between OSC1 and OSC2 is turned off in these modes to save current. There is no oscillator start-up time required after a Power-on Reset or after a recovery from SLEEP mode. In the EC oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 2-3 shows the pin connections for the EC oscillator mode. A Phase Lock Loop (PLL) circuit is provided as a software programmable option for users that want to multiply the frequency of the incoming crystal oscillator signal by 4. For an input clock frequency of 6 MHz, the internal clock frequency will be multiplied to 24 MHz. This is useful for customers who are concerned with EMI due to high frequency crystals. The PLL is enabled by configuring HS oscillator mode and setting the PLLEN bit in the OSCON register. If HS oscillator mode is not selected, or PLLEN bit in OSCCON register is clear, the PLL is not enabled and the system clock will come directly from OSC1. HS oscillator mode is the default for PIC18C601/801. In all other modes, the PLLEN bit and the SCS1 bit are forced to `0'. A PLL lock timer is used to ensure that the PLL has locked before device execution starts. The PLL lock timer has a time-out, referred to as TPLL. FIGURE 2-3: EXTERNAL CLOCK INPUT OPERATION (EC OSC CONFIGURATION) OSC1 PIC18C601/801 Clock from ext. system FOSC/4 OSC2 FIGURE 2-4: PLL BLOCK DIAGRAM HS Osc PLL Enable OSCOUT Phase Comparator Crystal Osc FIN Loop Filter FOUT Feedback Divider 3 2 1 0 MUX SYSCLK CVCO VCO OSCIN 2001 Microchip Technology Inc. Advance Information DS39541A-page 23 PIC18C601/801 2.6 Oscillator Switching Feature 2.6.1 SYSTEM CLOCK SWITCH BIT PIC18C601/801 devices include a feature that allows the system clock source to be switched from the main oscillator to an alternate low frequency clock source. For PIC18C601/801 devices, this alternate clock source is the Timer1 oscillator. If a low frequency crystal (32 kHz, for example) has been attached to the Timer1 oscillator pins and the Timer1 oscillator has been enabled, the device can switch to a low power execution mode. Figure 2-5 shows a block diagram of the system clock sources. The system clock source switching is performed under software control. The system clock switch bit, SCS0 (OSCCON register), controls the clock switching. When the SCS0 bit is '0', the system clock source comes from the main oscillator, selected by the FOSC2:FOSC0 configuration bits in CONFIG1H register. When the SCS0 bit is set, the system clock source will come from the Timer1 oscillator. The SCS0 bit is cleared on all forms of RESET. Note: The Timer1 oscillator must be enabled to switch the system clock source. The Timer1 oscillator is enabled by setting the T1OSCEN bit in the Timer1 control register (T1CON). If the Timer1 oscillator is not enabled, any write to the SCS0 bit will be ignored (SCS0 bit forced cleared) and the main oscillator will continue to be the system clock source. FIGURE 2-5: DEVICE CLOCK SOURCES PIC18C601/801 Main Oscillator OSC2 SLEEP OSC1 Timer 1 Oscillator T1OSO T1OSCEN Enable Oscillator Clock Source option for other modules 4 x PLL TOSC TOSC/4 TSCLK MUX TT1P Clock Source T1OSI Note: I/O pins have diode protection to VDD and VSS. DS39541A-page 24 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 REGISTER 2-1: OSCCON REGISTER U-0 -- bit 7 bit 7-4 bit 3 Unimplemented: Read as '0' LOCK: Phase Lock Loop Lock Status bit 1 = Phase Lock Loop output is stable as system clock 0 = Phase Lock Loop output is not stable and cannot be used as system clock PLLEN: Phase Lock Loop Enable bit 1 = Enable Phase Lock Loop output as system clock 0 = Disable Phase Lock Loop SCS1: System Clock Switch bit 1 When PLLEN and LOCK bit are set: 1 = Use PLL output 0 = Use primary oscillator/clock input pin When PLLEN bit or LOCK bit is cleared: Bit is forced clear SCS0: System Clock Switch bit 0 When T1OSCEN bit is set: 1 = Switch to Timer1 oscillator/clock pin 0 = Use primary oscillator/clock input pin When T1OSCEN is cleared: Bit is forced clear Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- R/W-0 LOCK R/W-0 PLLEN R/W-0 SCS1 R/W-0 SCS0 bit 0 bit 2 bit 1 bit 0 2.6.2 OSCILLATOR TRANSITIONS PIC18C601/801 devices contain circuitry to prevent "glitches" when switching between oscillator sources. Essentially, the circuitry waits for eight rising edges of the clock source that the processor is switching to. This ensures that the new clock source is stable and that its pulse width will not be less than the shortest pulse width of the two clock sources. A timing diagram indicating the transition from the main oscillator to the Timer1 oscillator is shown in Figure 2-6. The Timer1 oscillator is assumed to be running all the time. After the SCS0 bit is set, the processor is frozen at the next occurring Q1 cycle. After eight synchronization cycles are counted from the Timer1 oscillator, operation resumes. No additional delays are required after the synchronization cycles. The sequence of events that takes place when switching from the Timer1 oscillator to the main oscillator will depend on the mode of the main oscillator. In addition to eight clock cycles of the main oscillator, additional delays may take place. If the main oscillator is configured for an external crystal (HS, LP), the transition will take place after an oscillator start-up time (TOST) has occurred. A timing diagram indicating the transition from the Timer1 oscillator to the main oscillator for HS and LP modes is shown in Figure 2-7. 2001 Microchip Technology Inc. Advance Information DS39541A-page 25 PIC18C601/801 FIGURE 2-6: Q1 Q2 TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR Q3 Q4 Q1 TT1P 1 2 3 4 TSCS 5 6 7 8 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 T1OSI OSC1 TOSC Internal System Clock SCS0 (OSCCON<0>) Program Counter PC TDLY PC + 2 PC + 4 Note: Delay on internal system clock is eight oscillator cycles for synchronization. FIGURE 2-7: Q3 TIMING DIAGRAM FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, LP) Q4 Q1 TT1P Q1 Q2 Q3 Q4 Q1 Q2 Q3 T1OSI OSC1 TOST OSC2 Internal System Clock SCS0 (OSCCON<0>) TOSC 1 2 3 4 5 TSCS 6 7 8 Program Counter Note: PC PC + 2 PC + 4 TOST = 1024TOSC (drawing not to scale). DS39541A-page 26 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 If the main oscillator is configured for HS4 (PLL) mode with SCS1 bit set to `1', an oscillator start-up time (TOST), plus an additional PLL time-out (TPLL) will occur. The PLL time-out is typically 2 ms and allows the PLL to lock to the main oscillator frequency. A timing diagram indicating the transition from the Timer1 oscillator to the main oscillator for HS4 mode is shown in Figure 2-8. If the main oscillator is configured for HS4 (PLL) mode, with SCS1 bit set to `0', only oscillator start-up time (TOST) will occur. Since SCS1 bit is set to `0', PLL output is not used, so the system oscillator will come from OSC1 directly and additional delay of TPLL is not required. A timing diagram indicating the transition from the Timer1 oscillator to the main oscillator for HS4 mode is shown in Figure 2-9. If the main oscillator is configured in the RC or EC modes, there is no oscillator start-up time-out. Operation will resume after eight cycles of the main oscillator have been counted. A timing diagram indicating the transition from the Timer1 oscillator to the main oscillator for RC and EC modes is shown in Figure 2-10. FIGURE 2-8: Q4 TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS4 WITH SCS1 = 1) Q1 TT1P Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 T1OSI OSC1 TOST OSC2 PLL Clock Input Internal System Clock SCS0 (OSCCON<0>) Program Counter PC PC + 2 PC + 4 TOSC 1 2 3 TPLL TSCS 4 5 6 7 8 Note: TOST = 1024TOSC (drawing not to scale). FIGURE 2-9: Q4 TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS4 WITH SCS = 0) Q1 TT1P Q1 Q2 Q3 Q4 Q1 Q2 T1OSI OSC1 TOST OSC2 PLL Clock Output Internal System Clock SCS0 (OSCCON<0>) Program Counter Note: TDLY TPLL TSCS TOSC PC PC + 2 PC + 4 TOST = 1024TOSC (drawing not to scale). 2001 Microchip Technology Inc. Advance Information DS39541A-page 27 PIC18C601/801 FIGURE 2-10: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC) Q3 Q4 Q1 TT1P Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 T1OSI OSC1 OSC2 Internal System Clock SCS0 (OSCCON<0>) TOSC 1 2 3 4 5 6 7 8 TSCS Program Counter Note: RC oscillator mode assumed. PC PC + 2 PC + 4 2.6.3 SCS0, SCS1 PRIORITY If both SCS0 and SCS1 are set to `1' simultaneously, the SCS0 bit has priority over the SCS1 bit. This means that the low power option will take precedence over the PLL option. If both bits are cleared simultaneously, the system clock will come from OSC1, after a TOST timeout. If only the SCS0 bit is cleared, the system clock will come from the PLL output, following TOST and TPLL time. rent consumed during SLEEP. The user can wake from SLEEP through external RESET, Watchdog Timer Reset, or through an interrupt. 2.8 Power-up Delays TABLE 2-3: SCS1 0 0 1 1 SCS0 0 1 0 1 SCS0, SCS1 PRIORITY Clock Source Ext Oscillator OSC1 Timer1 Oscillator HS + PLL Timer1 Oscillator Power-up delays are controlled by two timers, so that no external RESET circuitry is required for most applications. The delays ensure that the device is kept in RESET until the device power supply and clock are stable. For additional information on RESET operation, see Section 3.0 RESET. The first timer is the Power-up Timer (PWRT), which optionally provides a fixed delay of TPWRT (parameter #33) on power-up only. The second timer is the Oscillator Start-up Timer (OST), intended to keep the chip in RESET until the crystal oscillator is stable. PIC18C601/801 devices provide a configuration bit, PWRTEN in CONFIG2L register, to enable or disable the Power-up Timer. By default, the Power-up Timer is enabled. With the PLL enabled (HS4 oscillator mode), the time-out sequence following a Power-on Reset is different from other oscillator modes. The time-out sequence is as follows: the PWRT time-out is invoked after a POR time delay has expired, then, the Oscillator Start-up Timer (OST) is invoked. However, this is still not a sufficient amount of time to allow the PLL to lock at high frequencies. The PWRT timer is used to provide an additional time-out, called TPLL (parameter #7), to allow the PLL ample time to lock to the incoming clock frequency. 2.7 Effects of SLEEP Mode on the On-Chip Oscillator When the device executes a SLEEP instruction, the on-chip clocks and oscillator are turned off and the device is held at the beginning of an instruction cycle (Q1 state). With the oscillator off, the OSC1 and OSC2 signals will stop oscillating. Since all the transistor switching currents have been removed, SLEEP mode achieves the lowest current consumption of the device (only leakage currents). Enabling any on-chip feature that will operate during SLEEP, will increase the cur- TABLE 2-4: OSC Mode OSC1 AND OSC2 PIN STATES IN SLEEP MODE OSC1 Pin OSC2 Pin RC Floating, external resistor should pull high At logic low EC Floating At logic low LP and HS Feedback inverter disabled, at quiescent voltage level Feedback inverter disabled, at quiescent voltage level Note: See Table 3-1 in Section 3.0 RESET, for time-outs due to SLEEP and MCLR Reset. DS39541A-page 28 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 3.0 RESET PIC18C601/801 devices differentiate between various kinds of RESET: a) b) c) d) e) f) g) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during SLEEP Watchdog Timer (WDT) Reset during normal operation RESET Instruction Stack Full Reset Stack Underflow Reset Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. Status bits from the RCON register, RI, TO, PD and POR, are set or cleared differently in different RESET situations, as indicated in Table 3-2. These bits are used in software to determine the nature of the RESET. See Table 3-3 for a full description of the RESET states of all registers. A simplified block diagram of the on-chip RESET circuit is shown in Figure 3-1. PIC18C601/801 has a MCLR noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. A WDT Reset does not drive MCLR pin low. Most registers are unaffected by a RESET. Their status is unknown on POR and unchanged by all other RESETS. The other registers are forced to a "RESET" state on Power-on Reset, MCLR, WDT Reset, MCLR Reset during SLEEP, and by the RESET instruction. FIGURE 3-1: RESET Instruction SIMPLIFIED BLOCK DIAGRAM OF THE ON-CHIP RESET CIRCUIT Stack Pointer Stack Full/Underflow Reset External Reset MCLR WDT Module VDD Rise Detect VDD SLEEP WDT Time-out Reset Power-on Reset S OST/PWRT OST 10-bit Ripple Counter OSC1 PWRT On-chip RC OSC(1) Chip_Reset R Q 10-bit Ripple Counter Enable PWRT Enable OST(2) Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin. 2: See Table 3-1 for time-out situations. 2001 Microchip Technology Inc. Advance Information DS39541A-page 29 PIC18C601/801 3.1 Power-on Reset (POR) 3.3 Oscillator Start-up Timer (OST) A Power-on Reset pulse is generated on-chip when a VDD rise is detected. To take advantage of the POR circuitry, connect the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset delay. A minimum rise rate for VDD is specified (parameter D004). For a slow rise time, see Figure 3-2. When the device starts normal operation (exits the RESET condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in RESET until the operating conditions are met. Power-on Reset may be used to meet the voltage start-up condition. The Oscillator Start-up Timer (OST) provides 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over (parameter #32). This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for LP, HS and HS4 modes and only on Power-on Reset or wake-up from SLEEP. 3.4 PLL Lock Time-out FIGURE 3-2: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) With the PLL enabled, the time-out sequence following a Power-on Reset is different from other oscillator modes. A portion of the Power-up Timer is used to provide a fixed time-out that is sufficient for the PLL to lock to the main oscillator frequency. This PLL lock time-out (TPLL) is typically 1 ms and follows the oscillator startup time-out (OST). VDD D R R1 MCLR C PIC18C601/801 3.5 Time-out Sequence Note 1: External Power-on Reset circuit is required only if the VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: R < 40 k is recommended to make sure that the voltage drop across R does not violate the device's electrical specification. 3: R1 = 100 to 1 k will limit any current flowing into MCLR from external capacitor C, in the event of MCLR/VPP pin breakdown due to Electrostatic Discharge (ESD), or Electrical Overstress (EOS). On power-up, the time-out sequence is as follows: First, PWRT time-out is invoked after the POR time delay has expired; then, OST is activated. The total time-out will vary based on oscillator configuration and the status of the PWRT. For example, in RC mode with the PWRT disabled, there will be no time-out at all. Figure 3-3, Figure 3-4, Figure 3-5, Figure 3-6 and Figure 3-7 depict time-out sequences on power-up. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Bringing MCLR high will begin execution immediately (Figure 3-5). This is useful for testing purposes or to synchronize more than one PIC18C601/801 device operating in parallel. Table 3-2 shows the RESET conditions for some Special Function Registers, while Table 3-3 shows the RESET conditions for all registers. 3.2 Power-up Timer (PWRT) The Power-up Timer provides a fixed nominal time-out (parameter #33), only on power-up from the POR. The Power-up Timer operates on an internal RC oscillator. The chip is kept in RESET as long as the PWRT is active. The PWRT time delay allows VDD to rise to an acceptable level. PIC18C601/801 devices are available with PWRT enabled or disabled. The power-up time delay will vary from chip to chip, due to VDD, temperature and process variation. See DC parameter #33 for details. DS39541A-page 30 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 TABLE 3-1: TIME-OUT IN VARIOUS SITUATIONS Power-up(2) PWRTEN = 0 72 ms + 1024TOSC 72 ms + 1024TOSC 72 ms 72 ms PWRTEN = 1 1024TOSC 1024TOSC -- -- Wake-up from SLEEP or Oscillator Switch(1) 1024TOSC + 1 ms 1024TOSC -- -- Oscillator Configuration HS with PLL enabled(1) HS, LP EC External RC Note 1: 1 ms is the nominal time required for the 4X PLL to lock. Maximum time is 2 ms. 2: 72 ms is the nominal Power-up Timer delay. REGISTER 3-1: RCON REGISTER BITS AND POSITIONS R/W-0 IPEN bit 7 U-0 r U-0 -- R/W-1 RI R/W-1 TO R/W-1 PD R/W-1 POR U-0 r bit 0 TABLE 3-2: STATUS BITS, THEIR SIGNIFICANCE, AND THE INITIALIZATION CONDITION FOR RCON REGISTER Condition Program Counter 00000h 00000h 00000h 00000h 00000h 00000h 00000h RCON Register 0r-1 110r 0r-u uuur 0r-0 uuur 0r-u uu1r 0r-u uu1r 0r-u 10ur 0r-u 01ur ur-u 00ur ur-u 00ur RI 1 u 0 u u u u u u TO 1 u u u u 1 0 0 0 PD 1 u u u u 0 1 0 0 POR 0 u u 1 1 u u u u STKFUL STKUNF u u u u 1 u u u u u u u 1 u u u u u Power-on Reset MCLR Reset during normal operation Software Reset during normal operation Stack Full Reset during normal operation Stack Underflow Reset during normal operation MCLR Reset during SLEEP WDT Reset WDT Wake-up Interrupt wake-up from SLEEP PC + 2 PC + 2(1) Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', r = reserved, maintain `0' Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (000008h or 000018h). 2001 Microchip Technology Inc. Advance Information DS39541A-page 31 PIC18C601/801 FIGURE 3-3: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) TOST OST TIME-OUT INTERNAL RESET FIGURE 3-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS39541A-page 32 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 FIGURE 3-6: SLOW RISE TIME (MCLR TIED TO VDD) 5V VDD MCLR INTERNAL POR 0V 1V TDEADTIME TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 3-7: TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED TO VDD) VDD MCLR IINTERNAL POR TPWRT PWRT TIME-OUT TOST TPLL OST TIME-OUT PLL TIME-OUT INTERNAL RESET TOST = 1024 clock cycles. TPLL 2 ms max. First three stages of the PWRT timer. 2001 Microchip Technology Inc. Advance Information DS39541A-page 33 PIC18C601/801 TABLE 3-3: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS Applicable Devices 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 Power-on Reset MCLR Reset WDT Reset Reset Instruction Stack Over/Underflow Reset ---0 0000 0000 0000 0000 0000 00-0 0000 ---0 0000 0000 0000 0000 0000 --00 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu 0000 000u 1111 -1-1 11-0 0-00 (Note 5) (Note 5) (Note 5) (Note 5) (Note 5) ---- 0000 uuuu uuuu uuuu uuuu (Note 5) (Note 5) (Note 5) (Note 5) (Note 5) ---- 0000 uuuu uuuu ---- 0000 (Note 5) Wake-up via WDT or Interrupt ---u uuuu(3) uuuu uuuu(3) uuuu uuuu(3) uu-u uuuu(3) ---u uuuu uuuu uuuu PC + 2(2) --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu(1) uuuu -u-u(1) uu-u u-uu(1) (Note 5) (Note 5) (Note 5) (Note 5) (Note 5) ---- uuuu uuuu uuuu uuuu uuuu (Note 5) (Note 5) (Note 5) (Note 5) (Note 5) ---- uuuu uuuu uuuu ---- uuuu (Note 5) TOSU TOSH TOSL STKPTR PCLATU PCLATH PCL TBLPTRU TBLPTRH TBLPTRL TABLAT PRODH PRODL INTCON INTCON2 INTCON3 INDF0 POSTINC0 POSTDEC0 PREINC0 PLUSW0 FSR0H FSR0L WREG INDF1 POSTINC1 POSTDEC1 PREINC1 PLUSW1 FSR1H FSR1L BSR INDF2 ---0 0000 0000 0000 0000 0000 00-0 0000 ---0 0000 0000 0000 0000 0000 --00 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx 0000 000x 1111 -1-1 11-0 0-00 (Note 5) (Note 5) (Note 5) (Note 5) (Note 5) ---- 0000 xxxx xxxx xxxx xxxx (Note 5) (Note 5) (Note 5) (Note 5) (Note 5) ---- 0000 xxxx xxxx ---- 0000 (Note 5) Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition, r = reserved, maintain `0' Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (00008h or 00018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH, and TOSL are updated with the current value of the PC. The SKPTR is modified to point to the next location in the hardware stack. 4: See Table 3-2 for RESET value for specific condition. 5: This is not a physical register. It is an indirect pointer that addresses another register. The contents returned is the value contained in the addressed register. DS39541A-page 34 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 TABLE 3-3: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 Power-on Reset MCLR Reset WDT Reset Reset Instruction Stack Over/Underflow Reset (Note 5) (Note 5) (Note 5) (Note 5) ---- 0000 uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu 1111 1111 --uu u-u0 --00 0101 ---- uuuu 0r-1 qqur uuuu uuuu uuuu uuuu u-uu uuuu uuuu uuuu 1111 1111 -000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu --00 0000 -000 0000 0--- -000 uuuu uuuu uuuu uuuu --00 0000 Wake-up via WDT or Interrupt (Note 5) (Note 5) (Note 5) (Note 5) ---- uuuu uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu u-uu --uu uuuu ---- uuuu ur-u qqur uuuu uuuu uuuu uuuu u-uu uuuu uuuu uuuu 1111 1111 -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu -uuu uuuu u--- -uuu uuuu uuuu uuuu uuuu --uu uuuu POSTINC2 POSTDEC2 PREINC2 PLUSW2 FSR2H FSR2L STATUS TMR0H TMR0L T0CON OSCCON LVDCON WDTCON RCON (4) (Note 5) (Note 5) (Note 5) (Note 5) ---- 0000 xxxx xxxx ---x xxxx xxxx xxxx xxxx xxxx 1111 1111 --00 0-00 --00 0101 ---- 1111 0r-1 11qr xxxx xxxx xxxx xxxx 0-00 0000 xxxx xxxx 1111 1111 -000 0000 xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx --00 0000 -000 0000 0--- -000 xxxx xxxx xxxx xxxx --00 0000 TMR1H TMR1L T1CON TMR2 PR2 T2CON SSPBUF SSPADD SSPSTAT SSPCON1 SSPCON2 ADRESH ADRESL ADCON0 ADCON1 ADCON2 CCPR1H CCPR1L CCP1CON Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition, r = reserved, maintain `0' Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (00008h or 00018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH, and TOSL are updated with the current value of the PC. The SKPTR is modified to point to the next location in the hardware stack. 4: See Table 3-2 for RESET value for specific condition. 5: This is not a physical register. It is an indirect pointer that addresses another register. The contents returned is the value contained in the addressed register. 2001 Microchip Technology Inc. Advance Information DS39541A-page 35 PIC18C601/801 TABLE 3-3: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 Power-on Reset MCLR Reset WDT Reset Reset Instruction Stack Over/Underflow Reset uuuu uuuu uuuu uuuu --00 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 -01u 0000 000u -1-- 1111 -1-- 0000 -1-- 0000 1111 1111 -111 1111 0000 0000 -000 0000 0000 0000 -000 0000 0000 --00 1111 1111 1111 1111 ---1 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 --11 1111 ---u uuuu uuuu uuuu uuuu uuuu Wake-up via WDT or Interrupt uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu -u-- uuuu -u-- uuuu(1) -u-- uuuu uuuu uuuu -uuu uuuu uuuu uuuu(1) -uuu uuuu(1) uuuu uuuu -uuu uuuu uuuu --uu uuuu uuuu uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu ---u uuuu uuuu uuuu uuuu uuuu CCPR2H CCPR2L CCP2CON TMR3H TMR3L T3CON SPBRG RCREG TXREG TXSTA RCSTA IPR2 PIR2 PIE2 IPR1 PIR1 PIE1 MEMCON TRISJ TRISH TRISG TRISF TRISE TRISD TRISC TRISB TRISA LATG LATF LATE xxxx xxxx xxxx xxxx --00 0000 xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx 0000 -01x 0000 000x -1-- 1111 -1-- 0000 -1-- 0000 1111 1111 -111 1111 0000 0000 -000 0000 0000 0000 -000 0000 0000 --00 1111 1111 1111 1111 ---1 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 --11 1111 ---x xxxx xxxx xxxx xxxx xxxx Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition, r = reserved, maintain `0' Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (00008h or 00018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH, and TOSL are updated with the current value of the PC. The SKPTR is modified to point to the next location in the hardware stack. 4: See Table 3-2 for RESET value for specific condition. 5: This is not a physical register. It is an indirect pointer that addresses another register. The contents returned is the value contained in the addressed register. DS39541A-page 36 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 TABLE 3-3: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices 601 601 601 601 601 601 601 601 601 601 601 601 601 601 601 801 801 801 801 801 801 801 801 801 801 801 801 801 801 801 Power-on Reset MCLR Reset WDT Reset Reset Instruction Stack Over/Underflow Reset uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu 0000 uuuu ---u uuuu uuuu u000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --0u 0000 uuuu uuuu uuuu uuuu Wake-up via WDT or Interrupt uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu LATD LATC LATB LATA PORTJ PORTH PORTG PORTF PORTE PORTD PORTC PORTB PORTA CSEL2 CSELIO xxxx xxxx xxxx xxxx xxxx xxxx --xx xxxx xxxx xxxx 0000 xxxx ---x xxxx xxxx x000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx --0x 0000 1111 1111 1111 1111 Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition, r = reserved, maintain `0' Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (00008h or 00018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH, and TOSL are updated with the current value of the PC. The SKPTR is modified to point to the next location in the hardware stack. 4: See Table 3-2 for RESET value for specific condition. 5: This is not a physical register. It is an indirect pointer that addresses another register. The contents returned is the value contained in the addressed register. 2001 Microchip Technology Inc. Advance Information DS39541A-page 37 PIC18C601/801 NOTES: DS39541A-page 38 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 4.0 MEMORY ORGANIZATION 4.1.1 "BOOT RAM" PROGRAM MEMORY There are two memory blocks in PIC18C601/801 devices. These memory blocks are: * Program Memory * Data Memory Each block has its own bus so that concurrent access can occur. PIC18C601/801 devices have a provision for configuring the last 512 bytes of general purpose user RAM as program memory, called "Boot RAM". This is achieved by configuring the PGRM bit in the MEMCON register to `1'. (Refer to Section 5.0, "External Memory Interface" for more information.) When the PGRM bit is `1', the RAM located in data memory locations 400h through 5FFh (bank 4 through 5) is mapped to program memory locations 1FFE00h to 1FFFFFh. When configured as program memory, the Boot RAM is to be used as a temporary "boot loader" for programming purposes. It can only be used for program execution. A read from locations 400h to 5FFh in data memory returns all `0's. Any attempt to write this RAM as data memory when PGRM = 1, does not modify any of these locations. TBLWT instructions to these locations will cause writes to occur on the external memory bus. The boot RAM program memory cannot be modified using TBLWT instruction. TBLRD instructions from boot RAM will read memory located on the external memory bus, not from the on-board RAM. Constants that are stored in boot RAM are retrieved using the RETLW instruction. The default RESET state (power-up) for the PGRM bit is `0', which configures 1.5K of data RAM and all program memory as external. The PGRM bit can be set and cleared in the software. When execution takes place from "Boot RAM", the external system bus and all of its control signals will be deactivated. If execution takes place from outside of "Boot RAM", the external system bus and all of its control signals are activated again. Figure 4-3 and Figure 4-4 show the program memory map and stack for PIC18C601 and PIC18C801, when the PGRM bit is set. 4.1 Program Memory Organization PIC18C601/801 devices have a 21-bit program counter that is capable of addressing up to 2 Mbyte of external program memory space. The PIC18C601 has an external program memory address space of 256 Kbytes. Any program fetch or TBLRD from a program location greater than 256K will return all NOPs. The PIC18C801 has an external program memory address space of 2Mbytes. Refer to Section 5.0 ("External Memory Interface") for additional details. The RESET vector address is mapped to 000000h and the interrupt vector addresses are at 000008h and 000018h. PIC18C601/801 devices have a 31-level stack to store the program counter values during subroutine calls and interrupts. Figure 4-1 shows the program memory map and stack for PIC18C601. Figure 4-2 shows the program memory map and stack for the PIC18C801. 2001 Microchip Technology Inc. Advance Information DS39541A-page 39 PIC18C601/801 FIGURE 4-1: PROGRAM MEMORY MAP AND STACK FOR PIC18C601 (PGRM = 0) 21 Stack Level 1 * * * FIGURE 4-2: PROGRAM MEMORY MAP AND STACK FOR PIC18C801 (PGRM = 0) PC<20:0> 21 PC<20:0> Stack Level 1 * * * Stack Level 31 RESET Vector 0000h Stack Level 31 RESET Vector 0000h High Priority Interrupt Vector 0008h Low Priority Interrupt Vector 0018h High Priority Interrupt Vector 0008h Low Priority Interrupt Vector 0018h User Memory Space External Program Memory 3FFFFh 40000h Read '0' 1FFFFFh 1FFFFFh DS39541A-page 40 Advance Information 2001 Microchip Technology Inc. User Memory Space External Program Memory PIC18C601/801 FIGURE 4-3: PROGRAM MEMORY MAP AND STACK FOR PIC18C601 (PGRM = 1) PC<20:0> 21 Stack Level 1 * * * Stack Level 31 RESET Vector 0000h High Priority Interrupt Vector 0008h Low Priority Interrupt Vector 0018h 03FFFFh 040000h Read '0' 1FFE00h 1FFDFFh 1FFE00h On-Chip Boot RAM 1FFFFFh 1FFFFFh INTERNAL MEMORY EXTERNAL MEMORY 2001 Microchip Technology Inc. Advance Information User Memory Space External Program Memory DS39541A-page 41 PIC18C601/801 FIGURE 4-4: PROGRAM MEMORY MAP AND STACK FOR PIC18C801 (PGRM = 1) PC<20:0> 21 Stack Level 1 * * * Stack Level 31 RESET Vector 0000h High Priority Interrupt Vector 0008h Low Priority Interrupt Vector 0018h External Program Memory 1FFE00h 1FFDFFh 1FFE00h On-Chip Boot RAM 1FFFFFh External Table Memory 1FFFFFh INTERNAL MEMORY EXTERNAL MEMORY DS39541A-page 42 Advance Information 2001 Microchip Technology Inc. User Memory Space PIC18C601/801 4.1.2 BOOT LOADER 4.2.1 TOP-OF-STACK ACCESS When configured as Program Memory, Boot RAM can be used as a temporary "Boot Loader" for programming purposes. If an external memory device is used as program memory, any updates performed by the user program will have to be performed in the "Boot RAM", because the user program cannot program and fetch from external memory, simultaneously. A typical boot loader execution and external memory programming sequence would be as follows: * The boot loader program is transferred from the external program memory to the last 2 banks of data RAM by TBLRD and MOVWF instructions. * Once the "boot loader" program is loaded into internal memory and verified, open combination lock and set PGRM bit to configure the data RAM into program RAM. * Jump to beginning of Boot code in Boot RAM. Program execution begins in Boot RAM to begin programming the external memory. System bus changes to an inactive state. * Boot loader program performs the necessary external TBLWT and TBLWRD instructions to perform programming functions. * When the boot loader program is finished programming external memory, jump to known valid external program memory location and clear PGRM bit in MEMCON register to set Boot RAM as data memory, or reset the part. The top of the stack is readable and writable. Three register locations, TOSU, TOSH and TOSL, allow access to the contents of the stack location indicated by the STKPTR register. This allows users to implement a software stack, if necessary. After a CALL, RCALL or interrupt, the software can read the pushed value by reading the TOSU, TOSH and TOSL registers. These values can be placed on a user defined software stack. At return time, the software can replace the TOSU, TOSH and TOSL and do a return. The user should disable the global interrupt enable bits during this time to prevent inadvertent stack operations. 4.2.2 RETURN STACK POINTER (STKPTR) The STKPTR register contains the stack pointer value, the STKFUL (stack full) status bit, and the STKUNF (stack underflow) status bits. Register 4-1 shows the STKPTR register. The value of the stack pointer can be 0 through 31. The stack pointer increments when values are pushed onto the stack and decrements when values are popped off the stack. At RESET, the stack pointer value will be 0. The user may read and write the stack pointer value. This feature can be used by a Real Time Operating System for return stack maintenance. After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is set. The STKFUL bit can only be cleared in software or by a POR. Any subsequent push operation that causes stack overflow will be ignored. The action that takes place when the stack becomes full, depends on the state of STVREN (stack overflow RESET enable) configuration bit in CONFIG4L register. Refer to Section 4.2.4 for more information. If STVREN is set (default), stack over/underflow will set the STKFUL bit, and reset the device. The STKFUL bit will remain set and the stack pointer will be set to 0. If STVREN is cleared, the STKFUL bit will be set on the 31st push and the stack pointer will increment to 31. All subsequent push attempts will be ignored and STKPTR remains at 31. When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the stack pointer remains at 0. The STKUNF bit will remain set until cleared in software, or a POR occurs. Note: Returning a value of zero to the PC on an underflow has the effect of vectoring the program to the RESET vector, where the stack conditions can be verified and appropriate actions can be taken. 4.2 Return Address Stack The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC (Program Counter) is pushed onto the stack when a PUSH, CALL or RCALL instruction is executed, or an interrupt is acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the return instructions. The stack operates as a 31-word by 21-bit stack memory and a five-bit stack pointer, with the stack pointer initialized to 00000b after all RESETS. There is no RAM associated with stack pointer 00000b. This is only a RESET value. During a CALL type instruction, causing a push onto the stack, the stack pointer is first incremented and the RAM location pointed to by the stack pointer is written with the contents of the PC. During a RETURN type instruction, causing a pop from the stack, the contents of the RAM location indicated by the STKPTR is transferred to the PC and then the stack pointer is decremented. The stack space is not part of either program or data space. The stack pointer is readable and writable, and the data on the top of the stack is readable and writable through SFR registers. Status bits STKOVF and STKUNF in STKPTR register, indicate whether stack over/underflow has occurred or not. 2001 Microchip Technology Inc. Advance Information DS39541A-page 43 PIC18C601/801 REGISTER 4-1: STKPTR - STACK POINTER REGISTER R/C-0 STKFUL bit 7 bit 7 R/C-0 STKUNF U-0 -- R/W-0 SP4 R/W-0 SP3 R/W-0 SP2 R/W-0 SP1 R/W-0 SP0 bit 0 STKFUL: Stack Full Flag bit 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed STKUNF: Stack Underflow Flag bit 1 = Stack underflow occurred 0 = Stack underflow did not occur Unimplemented: Read as '0' SP4:SP0: Stack Pointer Location bits Note: Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared C = Clearable bit Bit 7 and bit 6 can only be cleared in user software, or by a POR. bit 6 bit 5 bit 4-0 FIGURE 4-5: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Return Address Stack 11111 11110 11101 TOSU 00h TOSH 1Ah TOSL 34h Top-of-Stack STKPTR<4:0> 00010 00011 001A34h 00010 000D58h 00001 000000h 00000(1) Note 1: No RAM is associated with this address; always maintained `0's. DS39541A-page 44 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 4.2.3 PUSH AND POP INSTRUCTIONS 4.3 Fast Register Stack Since the Top-of-Stack (TOS) is readable and writable, the ability to push values onto the stack and pop values off the stack, without disturbing normal program execution, is a desirable option. To push the current PC value onto the stack, a PUSH instruction can be executed. This will increment the stack pointer and load the current PC value onto the stack. TOSU, TOSH and TOSL can then be modified to place a return address on the stack. The POP instruction discards the current TOS by decrementing the stack pointer. The previous value pushed onto the stack then becomes the TOS value. A "fast return" option is available for interrupts and calls. A fast register stack is provided for the STATUS, WREG and BSR registers, and is only one layer in depth. The stack is not readable or writable and is loaded with the current value of the corresponding register when the processor vectors for an interrupt. The values in the fast register stack are then loaded back into the working registers, if the fast return instruction is used to return from the interrupt. A low or high priority interrupt source will push values into the stack registers. If both low and high priority interrupts are enabled, the stack registers cannot be used reliably for low priority interrupts. If a high priority interrupt occurs while servicing a low priority interrupt, the stack register values stored by the low priority interrupt will be overwritten. If high priority interrupts are not disabled during low priority interrupts, users must save the key registers in software during a low priority interrupt. If no interrupts are used, the fast register stack can be used to restore the STATUS, WREG and BSR registers at the end of a subroutine call. To use the fast register stack for a subroutine call, a fast call instruction must be executed. Example 4-1 shows a source code example that uses the fast register stack. 4.2.4 STACK FULL/UNDERFLOW RESETS These RESETS are enabled/disabled by programming the STVREN configuration bit in CONFIG4L register. When the STVREN bit is disabled, a full or underflow condition will set the appropriate STKFUL or STKUNF bit, but not cause a RESET. When the STVREN bit is enabled, a full or underflow will set the appropriate STKFUL or STKUNF bit and then cause a RESET. The STKFUL or STKUNF bits are only cleared by the user software or a POR. EXAMPLE 4-1: CALL SUB1, FAST FAST REGISTER STACK CODE EXAMPLE ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER ;STACK * * SUB1 * * * RETURN FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK 2001 Microchip Technology Inc. Advance Information DS39541A-page 45 PIC18C601/801 4.4 PCL, PCLATH and PCLATU The program counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21-bits wide. The low byte is called the PCL register. This register is readable and writable. The high byte is called the PCH register. This register contains the PC<15:8> bits and is not directly readable or writable. Updates to the PCH register may be performed through the PCLATH register. The upper byte is called PCU. This register contains the PC<20:16> bits and is not directly readable or writable. Updates to the PCU register may be performed through the PCLATU register. The PC addresses bytes in the program memory. To prevent the PC from becoming misaligned with word instructions, the LSb of the PCL is fixed to a value of '0'. The PC increments by 2 to address sequential instructions in the program memory. The CALL, RCALL, GOTO and program branch instructions write to the program counter directly. For these instructions, the contents of PCLATH and PCLATU are not transferred to the program counter. The contents of PCLATH and PCLATU will be transferred to the program counter by an operation that writes PCL. Similarly, the upper two bytes of the program counter will be transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed offsets to the PC (See Section 4.8.1). 4.5 Clocking Scheme/Instruction Cycle The clock input (from OSC1 or PLL output) is internally divided by four to generate four non-overlapping quadrature clocks, namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 4-6. FIGURE 4-6: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Q3 Q4 PC OSC2/CLKOUT (RC mode) Internal Phase Clock PC Fetch INST (PC) Execute INST (PC-2) PC+2 PC+4 Fetch INST (PC+2) Execute INST (PC) Fetch INST (PC+4) Execute INST (PC+2) DS39541A-page 46 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 4.6 Instruction Flow/Pipelining 4.7 Instructions in Program Memory An "Instruction Cycle" consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined, such that fetch takes one instruction cycle, while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO), two cycles are required to complete the instruction (Example 4-2). A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the "Instruction Register" (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSB = '0'). Figure 4-1 shows an example of how instruction words are stored in the program memory. To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSB will always read '0' (see Section 4.4). The CALL and GOTO instructions have an absolute program memory address embedded into the instruction. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC<20:1>, which accesses the desired byte address in program memory. Instruction #2 in Figure 4-1 shows how the instruction "GOTO 0x06" is encoded in the program memory. Program branch instructions that encode a relative address offset operate in the same manner. The offset value stored in a branch instruction represents the number of single word instructions by which the PC will be offset. Section 20.0 provides further details of the instruction set. EXAMPLE 4-2: INSTRUCTION PIPELINE FLOW TCY0 TCY1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1 TCY2 TCY3 TCY4 TCY5 1. MOVLW 55h 2. MOVWF PORTB 3. BRA SUB_1 4. BSF Fetch 1 PORTA, BIT3 (Forced NOP) 5. Instruction @ address SUB_1 All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction is "flushed" from the pipeline, while the new instruction is being fetched and then executed. TABLE 4-1: INSTRUCTIONS IN PROGRAM MEMORY Opcode -- 0E55h EF03h, F000h Memory -- 55h 0Eh 03h EFh 00h F0h Address 000007h 000008h 000009h 00000Ah 00000Bh 00000Ch 00000Dh 00000Eh 00000Fh 000010h 000011h 000012h Instruction -- MOVLW 055h GOTO 000006h MOVFF 123h, 456h C123h, F456h 23h C1h 56h F4h -- -- -- 2001 Microchip Technology Inc. Advance Information DS39541A-page 47 PIC18C601/801 4.7.1 TWO-WORD INSTRUCTIONS PIC18C601/801 devices have four two-word instructions: MOVFF, CALL, GOTO and LFSR. The second word of these instructions has the four MSB's set to 1's and is a special kind of NOP instruction. The lower 12 bits of the second word contain data to be used by the instruction. If the first word of the instruction is executed, the data in the second word is accessed. If the second word of the instruction is executed by itself (first word was skipped), it will execute as a NOP. This action is necessary when the two-word instruction is preceded by a conditional instruction that changes the PC and skips one instruction. A program example that demonstrates this concept is shown in Example 4-3. Refer to Section 19.0 for further details of the instruction set. The offset value (value in WREG) specifies the number of bytes that the program counter should advance. In this method, only one data byte may be stored in each instruction location and room on the return address stack is required. Warning: The LSb of the PCL is fixed to a value of `0'. Hence, computed GOTO to an odd address is not possible. 4.8.2 TABLE READS/TABLE WRITES A better method of storing data in program memory allows 2 bytes of data to be stored in each instruction location. Lookup table data may be stored as 2 bytes per program word by using table reads and writes. The table pointer (TBLPTR) specifies the byte address and the table latch (TABLAT) contains the data that is read from, or written to, program memory. Data is transferred to/from program memory one byte at a time. A description of the Table Read/Table Write operation is shown in Section 6.0. Note: If execution is taking place from Boot RAM Program Memory, RETLW instructions must be used to read lookup values from the Boot RAM itself. 4.8 Lookup Tables Lookup tables are implemented two ways: * Computed GOTO * Table Reads 4.8.1 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). A lookup table can be formed with an ADDWF PCL instruction and a group of RETLW 0xnn instructions. WREG is loaded with an offset into the table, before executing a call to that table. The first instruction of the called routine is the ADDWF PCL instruction. The next instruction executed will be one of the RETLW 0xnn instructions that returns the value 0xnn to the calling function. EXAMPLE 4-3: Object Code Two-Word Instructions CASE 1: Source Code TSTFSZ MOVFF ADDWF REG1 REG1, REG2 REG3 ; is RAM location 0? ; No, execute 2-word instruction ; 2nd operand holds address of REG2 ; continue code 0110 0110 0000 0000 1100 0001 0010 0011 1111 0100 0101 0110 0010 0100 0000 0000 CASE 2: Object Code 0110 0110 0000 0000 1100 0001 0010 0011 1111 0100 0101 0110 0010 0100 0000 0000 ADDWF REG3 TSTFSZ MOVFF REG1 REG1, REG2 ; Yes ; 2nd operand executed as NOP ; continue code Source Code ; is RAM location 0? DS39541A-page 48 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 4.9 Data Memory Organization 4.9.1 The data memory is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. Figure 4-8 shows the data memory organization for PIC18C601/801 devices. The data memory map is divided into banks that contain 256 bytes each. The lower four bits of the Bank Select Register (BSR<3:0>) select which bank will be accessed. The upper 4 bits for the BSR are not implemented. The data memory contains Special Function Registers (SFR) and General Purpose Registers (GPR). The SFR's are used for control and status of the controller and peripheral functions, while GPR's are used for data storage and scratch pad operations in the user's application. The SFR's start at the last location of Bank 15 (0FFFh) and grow downwards. GPR's start at the first location of Bank 0 and grow upwards. Any read of an unimplemented location will read as '0's. GPR banks 4 and 5 serve as a Program Memory called "Boot RAM", when PGRM bit in MEMCON is set. When PGRM bit is set, any read from "Boot RAM" returns `0's, while any write to it is ignored. The entire data memory may be accessed directly or indirectly. Direct addressing may require the use of the BSR register. Indirect addressing requires the use of a File Select Register (FSR). Each FSR holds a 12-bit address value that can be used to access any location in the Data Memory map without banking. The instruction set and architecture allow operations across all banks. This may be accomplished by indirect addressing, or by the use of the MOVFF instruction. The MOVFF instruction is a two-word/two-cycle instruction that moves a value from one register to another. To ensure that commonly used registers (SFRs and select GPRs) can be accessed in a single cycle, regardless of the current BSR values, an Access Bank is implemented. A segment of Bank 0 and a segment of Bank 15 comprise the Access bank. Section 4.10 provides a detailed description of the Access bank. GENERAL PURPOSE REGISTER FILE The register file can be accessed either directly or indirectly. Indirect addressing operates through the File Select Registers (FSR). The operation of indirect addressing is shown in Section 4.12. PIC18C601/801 devices have banked memory in the GPR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other RESETS. Data RAM is available for use as GPR registers by all instructions. Bank 15 (0F80h to 0FFFh) contains SFR's. All other banks of data memory contain GPR registers starting with bank 0. 4.9.2 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is given in Table 4-2. The SFR's can be classified into two sets: those associated with the "core" function and those related to the peripheral functions. Those registers related to the "core" are described in this section, while those related to the operation of the peripheral features are described in the section of that peripheral feature. The SFRs are typically distributed among the peripherals whose functions they control. The unused SFR locations are unimplemented and read as '0's. See Table 4-2 for addresses for the SFRs. 4.9.3 SECURED ACCESS REGISTERS PIC18C601/801 devices contain software programming options for safety critical peripherals. Because these safety critical peripherals can be programmed in software, registers used to control these peripherals are given limited access by the user code. This way, errant code will not accidentally change settings in peripherals that could cause catastrophic results. The registers that are considered safety critical are the Watchdog Timer register (WDTCON), the External Memory Control register (MEMCON), the Oscillator Control register (OSCCON) and the Chip Select registers (CSSEL2 and CSELIO). Two bits called Combination Lock (CMLK) bits, located in the lower two bits of the PSPCON register, must be set in sequence by user code to gain access to Secured Access registers. 2001 Microchip Technology Inc. Advance Information DS39541A-page 49 PIC18C601/801 REGISTER 4-2: PSPCON REGISTER U-0 -- bit 7 bit 7-2 bit 1-0 Unimplemented: Read as '0' CMLK<1:0>: Combination Lock bits Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- W-0 CMLK1 W-0 CMLK0 bit 0 The Combination Lock bits must be set sequentially, meaning that as soon as Combination Lock bit CMLK1 is set, the second Combination Lock bit CMLK0 must be set on the following instruction cycle. If user waits more than one machine cycle to set the second bit after setting the first, both bits will automatically be cleared in hardware and the lock will remain closed. To satisfy this condition, all interrupts must be disabled before attempting to unlock the Combination Lock. Once secured registers are modified, interrupts may be re-enabled. Each instruction must only modify one combination lock bit at a time. This means, user code must use the BSF instruction to set CMLK bits in the PSPCON register. Note: The Combination Lock bits are write-only bits. These bits will always return `0' when read. When the Combination Lock is opened, the user will have three instruction cycles to modify the safety critical register of choice. After three instruction cycles have expired, the CMLK bits are cleared, the lock will close and the user will have to set the CMLK bits again, in order to open the lock. Since there are only three instruction cycles allowed after the Combination Lock is opened, if a subroutine is used to unlock Combination Lock bits, user code must preload WREG with the desired value, call unlock subroutine, and write to the desired safety critical register itself. Note: Successive attempts to unlock the Combination Lock must be separated by at least three instruction cycles. EXAMPLE 4-4: COMBINATION UNLOCK SUBROUTINE EXAMPLE CODE ; ; ; ; Preload WREG with data to be stored in a safety critical register Disable all interrupts Now unlock it Write must take place in next instruction cycle MOVLW 5Ah BCF INTCON, GIE CALL UNLOCK MOVWF OSCCON BSF INTCON, GIE * * UNLOCK BSF PSPCON, CMLK1 BSF PSPCON, CMLK0 RETURN * * ; Lock is closed ; Re-enable interrupts DS39541A-page 50 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 EXAMPLE 4-5: COMBINATION UNLOCK MACRO EXAMPLE CODE MACRO BCF INTCON, BSF PSPCON, BSF PSPCON, MOVWF @REG BSF INTCON, ENDM GIE CMLK1 CMLK0 GIE ; Disable interrupts UNLOCK_N_MODIFY @REG ; Modify given register ; Enable interrupts * * MOVLW 5Ah UNLOCK_N_MODIFY OSCCON ; Preload WREG for OSCCON register ; Modify OSCCON FIGURE 4-7: BSR<3:0> = 0000b THE DATA MEMORY MAP FOR PIC18C801/601 (PGRM = 0) Data Memory Map 00h Bank 0 FFh 00h Bank 1 FFh 00h Bank 2 FFh 00h Bank 3 FFh 00h Bank 4 FFh 00h GPR 3FFh 400h GPR 4FFh 500h GPR FFh 5FFh Access RAM Bank 00h Access Bank Low (GPR's) 7Fh Access Bank High 80h (SFR's) FFh Access GPR's GPR GPR 1FFh 200h GPR 2FFh 300h 000h 07Fh 080h 0FFh 100h = 0001b = 0010b = 0011b = 0100b = 0101b Bank 5 = 0110b = 1110b Bank 6 to Bank 14 Unused Read '00h' = 1111b 00h Bank 15 FFh Unused Access SFR's EFFh F00h F7Fh F80h FFFh When a = 0, the BSR is ignored and this Access RAM bank is used. The first 128 bytes are General Purpose RAM (from Bank 0). The next 128 bytes are Special Function Registers (from Bank 15). When a = 1, the BSR is used to specify the RAM location that the instruction uses. 2001 Microchip Technology Inc. Advance Information DS39541A-page 51 PIC18C601/801 FIGURE 4-8: BSR<3:0> = 0000b 00h Bank 0 FFh 00h Bank 1 FFh 00h Bank 2 = 0011b FFh 00h Bank 3 FFh GPR 3FFh Access RAM Bank 00h Access Bank Low (GPR's) 7Fh Access Bank High 80h (SFR's) FFh = 0100b = 1110b Bank 4 to Bank 14 Unused Read '00h' When a = 0, the BSR is ignored and this Access RAM bank is used. The first 128 bytes are General Purpose RAM (from Bank 0). The next 128 bytes are Special Function Registers (from Bank 15). DATA MEMORY MAP FOR PIC18C601/801 (PGRM = 1) Data Memory Map Access GPR's GPR GPR 1FFh 200h GPR 2FFh 300h 000h 07Fh 080h 0FFh 100h = 0001b = 0010b = 1111b 00h Bank 15 FFh Unused Access SFR's EFFh F00h F7Fh F80h FFFh When a = 1, the BSR is used to specify the RAM location that the instruction uses. DS39541A-page 52 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 FIGURE 4-9: FFFh FFEh FFDh FFCh FFBh FFAh FF9h FF8h FF7h FF6h FF5h FF4h FF3h FF2h FF1h FF0h FEFh FEEh FEDh FECh FEBh FEAh FE9h FE8h FE7h FE6h FE5h FE4h FE3h FE2h FE1h FE0h SPECIAL FUNCTION REGISTER MAP TOSU TOSH TOSL STKPTR PCLATU PCLATH PCL TBLPTRU TBLPTRH TBLPTRL TABLAT PRODH PRODL INTCON INTCON2 INTCON3 INDF0 POSTINC0 POSTDEC0 PREINC0 PLUSW0 FSR0H FSR0L WREG INDF1 POSTINC1 POSTDEC1 PREINC1 PLUSW1 FSR1H FSR1L BSR FDFh FDEh FDDh FDCh FDBh FDAh FD9h FD8h FD7h FD6h FD5h FD4h FD3h FD2h FD1h FD0h FCFh FCEh FCDh FCCh FCBh FCAh FC9h FC8h FC7h FC6h FC5h FC4h FC3h FC2h FC1h FC0h INDF2 POSTINC2 POSTDEC2 PREINC2 PLUSW2 FSR2H FSR2L STATUS TMR0H TMR0L T0CON Reserved OSCCON LVDCON WDTCON RCON TMR1H TMR1L T1CON TMR2 PR2 T2CON SSPBUF SSPADD SSPSTAT SSPCON1 SSPCON2 ADRESH ADRESL ADCON0 ADCON1 ADCON2 FBFh FBEh FBDh FBCh FBBh FBAh FB9h FB8h FB7h FB6h FB5h FB4h FB3h FB2h FB1h FB0h FAFh FAEh FADh FACh FABh FAAh FA9h FA8h FA7h FA6h FA5h FA4h FA3h FA2h FA1h FA0h CCPR1H CCPR1L CCP1CON CCPR2H CCPR2L CCP2CON Reserved Reserved Reserved -- -- -- TMR3H TMR3L T3CON PSPCON SPBRG RCREG TXREG TXSTA RCSTA -- -- -- CSEL2 CSELIO -- -- -- IPR2 PIR2 PIE2 F9Fh F9Eh F9Dh F9Ch F9Bh F9Ah F99h F98h F97h F96h F95h F94h F93h F92h F91h F90h F8Fh F8Eh F8Dh F8Ch F8Bh F8Ah F89h F88h F87h F86h F85h F84h F83h F82h F81h F80h IPR1 PIR1 PIE1 MEMCON -- TRISJ TRISH TRISG TRISF TRISE TRISD TRISC TRISB TRISA LATJ LATH LATG LATF LATE LATD LATC LATB LATA PORTJ PORTH PORTG PORTF PORTE PORTD PORTC PORTB PORTA 2001 Microchip Technology Inc. Advance Information DS39541A-page 53 PIC18C601/801 TABLE 4-2: File Name FFFh FFEh FFDh FFCh FFBh FFAh FF9h FF8h FF7h FF6h FF5h FF4h FF3h FF2h FF1h FF0h FEFh FEEh FEDh FECh FEBh FEAh FE9h FE8h FE7h FE6h FE5h FE4h FE3h FE2h FE1h FE0h FDFh FDEh FDDh FDCh FDBh FDAh FD9h FD8h Legend TOSU TOSH TOSL STKPTR PCLATU PCLATH PCL TBLPTRU TBLPTRH TBLPTRL TABLAT PRODH PRODL INTCON INTCON2 INTCON3 INDF0 POSTINC0 POSTDEC0 PREINC0 PLUSW0 FSR0H FSR0L WREG INDF1 POSTINC1 POSTDEC1 PREINC1 PLUSW1 FSR1H FSR1L BSR INDF2 POSTINC2 POSTDEC2 PREINC2 PLUSW2 FSR2H FSR2L STATUS REGISTER FILE SUMMARY - PIC18C601/801 Bit 7 -- Bit 6 -- Bit 5 -- Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Value on all other RESETS(1) Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 ---0 0000 0000 0000 0000 0000 0000 0000 0000 0000 Top-of-Stack High Byte (TOS<15:8>) Top-of-Stack Low Byte (TOS<7:0>) STKOVF -- STKUNF -- -- -- Return Stack Pointer Holding Register for PC<20:16> 00-0 0000 00-0 0000 ---0 0000 ---0 0000 0000 0000 0000 0000 0000 0000 0000 0000 Holding Register for PC<15:8> PC Low Byte (PC<7:0>) -- -- r Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --r0 0000 --r0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu Program Memory Table Pointer High Byte (TBLPTR<15:8>) Program Memory Table Pointer Low Byte (TBLPTR<7:0>) Program Memory Table Latch Product Register High Byte Product Register Low Byte GIE/GIEH RBPU INT2P PEIE/GIEL INTEDG0 INT1P TMR0IE INTEDG1 -- INT0E INTEDG2 INT2E RBIE -- INT1E TMR0IF T0IP -- INT0F -- INT2F RBIF RBIP INT1F 0000 000x 0000 000u 1111 -1-1 1111 -1-1 11-0 0-00 11-0 0-00 Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 post-decremented (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) Uses contents of FSR0 to address data memory -value of FSR0 offset by WREG (not a physical register) -- -- -- -- Indirect Data Memory Address Pointer 0 High N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A ---- xxxx ---- uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu Indirect Data Memory Address Pointer 0 Low Byte Working Register Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 post-decremented (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 offset by WREG (not a physical register) -- -- -- -- Indirect Data Memory Address Pointer 1 High N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A ---- xxxx ---- uuuu xxxx xxxx uuuu uuuu Indirect Data Memory Address Pointer 1 Low Byte -- -- -- -- Bank Select Register ---- 0000 ---- 0000 Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 post-decremented (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) Uses contents of FSR2 to address data memory -value of FSR2 offset by WREG (not a physical register) -- -- -- -- Indirect Data Memory Address Pointer 2 High N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A ---- xxxx ---- uuuu xxxx xxxx uuuu uuuu Indirect Data Memory Address Pointer 2 Low Byte -- -- -- N OV Z DC C ---x xxxx ---u uuuu x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved Note 1: Other (non-power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset. 2: These registers can only be modified when the Combination Lock is open. 3: These registers are available on PIC18C801 only. DS39541A-page 54 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 TABLE 4-2: File Name FD7h FD6h FD5h FD4h FD3h FD2h FD1h FD0h FCFh FCEh FCDh FCCh FCBh FCAh FC9h FC8h FC7h FC6h FC5h FC4h FC3h FC2h FC1h FC0h FBFh FBEh FBDh FBCh FBBh FBAh FB9h FB8h FB7h FB6h FB5h FB4h FB3h FB2h FB1h Legend TMR3H TMR3L T3CON Timer3 Register High Byte Timer3 Register Low Byte RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu REGISTER FILE SUMMARY - PIC18C601/801 (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Value on all other RESETS(1) TMR0H TMR0L T0CON Reserved OSCCON(2) LVDCON(2) WDTCON(2) RCON TMR1H TMR1L T1CON TMR2 PR2 T2CON SSPBUF SSPADD SSPSTAT SSPCON1 SSPCON2 ADRESH ADRESL ADCON0 ADCON1 ADCON2 CCPR1H CCPR1L CCP1CON CCPR2H CCPR2L CCP2CON Reserved Reserved Reserved Timer0 Register High Byte Timer0 Register Low Byte TMR0ON 16BIT T0CS T0SE T0PS3 T0PS2 T0PS1 T0PS0 0000 0000 0000 0000 xxxx xxxx uuuu uuuu 1111 1111 1111 1111 rrrr rrrr rrrr rrrr -- -- -- IPEN -- -- -- r -- IRVST -- -- -- LVDEN -- RI LOCK LVV3 WDPS2 TO PLLEN LVV2 WDPS1 PD SCS1 LVV1 WDPS0 POR SCS0 LVV0 ---- 0000 ---- uuu0 --00 0101 --00 0101 SWDTEN ---- 0000 ---- xxxx r 00-1 11qq 00-q qquu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu Timer1 Register High Byte Timer1 Register Low Byte RD16 Timer2 Register Timer2 Period Register -- TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 -- T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu 0000 0000 0000 0000 1111 1111 1111 1111 T2CKPS0 -000 0000 -000 0000 xxxx xxxx uuuu uuuu SSP Receive Buffer/Transmit Register SSP Address Register in SMP WCOL GCEN CKE SSPOV ACKSTAT I 2C Slave Mode. SSP Baud Rate Reload Register in D/A SSPEN ACKDT P CKP ACKEN S SSPM3 RCEN R/W SSPM2 PEN I2C Master Mode UA SSPM1 RSEN BF SSPM0 SEN 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu A/D Result Register High Byte A/D Result Register Low Byte -- -- ADFM -- -- -- CHS3 VCFG1 -- CHS2 VCFG0 -- CHS1 PCFG3 -- CHS0 PCFG2 ADCS2 GO/DONE PCFG1 ADCS1 ADON PCFG0 ADCS0 --00 0000 --00 0000 --00 0000 --00 0000 0--- -000 0--- -000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu Capture/Compare/PWM Register1 High Byte Capture/Compare/PWM Register1 Low Byte -- -- DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu Capture/Compare/PWM Register2 High Byte Capture/Compare/PWM Register2 Low Byte -- -- DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --uu uuuu rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr TMR3ON 0000 0000 uuuu uuuu x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved Note 1: Other (non-power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset. 2: These registers can only be modified when the Combination Lock is open. 3: These registers are available on PIC18C801 only. 2001 Microchip Technology Inc. Advance Information DS39541A-page 55 PIC18C601/801 TABLE 4-2: File Name FB0h FAFh FAEh FADh FACh FABh FAAh FA9h FA8h FA7h FA6h FA5h FA4h FA3h FA2h FA1h FA0h F9Fh F9Eh F9Dh F9Ch F9Bh F9Ah F99h F98h F96h F96h F95h F94h F93h F92h F91h F90h F8Fh F8Eh F8Dh F8Ch F8Bh F8Ah F89h F88h F87h F86h F85h Legend TRISJ(3) TRISH(3) TRISG TRISF TRISE TRISD TRISC TRISB TRISA LATJ (3) REGISTER FILE SUMMARY - PIC18C601/801 (CONTINUED) Bit 7 -- Bit 6 -- Bit 5 -- Bit 4 -- Bit 3 -- Bit 2 -- Bit 1 CMLK1 Bit 0 CMLK0 Value on POR Value on all other RESETS(1) PSPCON SPBRG RCREG TXREG TXSTA RCSTA ---- --00 ---- --00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 USART Baud Rate Generator USART Receive Register USART Transmit Register CSRC SPEN TX9 RX9 TXEN SREN SYNC CREN -- ADEN BRGH FERR TRMT OERR TX9D RX9D 0000 -010 0000 -010 0000 000x 0000 000x CSEL2(2) CSELIO(2) CSL7 CSIO7 CSL6 CSIO6 CSL5 CSIO5 CSL4 CSIO4 CSL3 CSIO3 CSL2 CSIO2 CSL1 CSIO1 CSL0 CSIO0 1111 1111 uuuu uuuu 1111 1111 uuuu uuuu IPR2 PIR2 PIE2 IPR1 PIR1 PIE1 MEMCON(2) -- -- -- -- -- -- EBDIS -- -- -- ADIP ADIF ADIE PGRM -- -- -- RCIP RCIF RCIE WAIT1 -- -- -- TXIP TXIF TXIE WAIT0 BCLIP BCLIF BCLIE SSPIP SSPIF SSPIE -- LVDIP LVDIF LVDIE CCP1IP CCP1IF CCP1IE -- TMR3IP TMR3IF TMR3IE TMR2IP TMR2IF TMR2IE WM1 CCP2IP CCP2IF CCP2IE TMR1IP TMR1IF TMR1IE WM0 ---- 1111 ---- 1111 ---- 0000 ---- 0000 ---- 0000 ---- 0000 -111 1111 -111 1111 -000 0000 -000 0000 -000 0000 -000 0000 0000 --00 0000 --00 Data Direction Control Register for PORTJ Data Direction Control Register for PORTH -- -- -- Read PORTG Data Latch, Write PORTG Data Latch 1111 1111 1111 1111 1111 1111 1111 1111 ---1 1111 ---1 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 --11 1111 --11 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu ---x xxxx ---u uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu --xx xxxx --uu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu ---x xxxx ---u uuuu xxxx xx00 uuuu uu00 Read PORTF Data Latch, Write PORTF Data Latch Data Direction Control Register for PORTE Data Direction Control Register for PORTD Data Direction Control Register for PORTC Data Direction Control Register for PORTB -- -- Data Direction Control Register for PORTA Read PORTJ Data Latch, Write PORTJ Data Latch Read PORTH Data Latch, Write PORTH Data Latch -- -- -- Read PORTG Data Latch, Write PORTG Data Latch LATH(3) LATG LATF LATE LATD LATC LATB LATA PORTJ(3) PORTH(3) PORTG PORTF Read PORTF Data Latch, Write PORTF Data Latch Read PORTE Data Latch, Write PORTE Data Latch Read PORTD Data Latch, Write PORTD Data Latch Read PORTC Data Latch, Write PORTC Data Latch Read PORTB Data Latch, Write PORTB Data Latch -- -- Read PORTA Data Latch, Write PORTA Data Latch Read PORTJ Pins, Write PORTJ Data Latch Read PORTH pins, Write PORTH Data Latch -- -- -- Read PORTG pins, Write PORTG Data Latch Read PORTF pins, Write PORTF Data Latch x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved Note 1: Other (non-power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset. 2: These registers can only be modified when the Combination Lock is open. 3: These registers are available on PIC18C801 only. DS39541A-page 56 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 TABLE 4-2: File Name F84h F83h F82h F81h F80h Legend PORTE PORTD PORTC PORTB PORTA REGISTER FILE SUMMARY - PIC18C601/801 (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Value on all other RESETS(1) Read PORTE Pins, Write PORTE Data Latch Read PORTD pins, Write PORTD Data Latch Read PORTC pins, Write PORTC Data Latch Read PORTB pins, Write PORTB Data Latch -- -- Read PORTA pins, Write PORTA Data Latch xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu --0x 0000 --0u 0000 x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved Note 1: Other (non-power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset. 2: These registers can only be modified when the Combination Lock is open. 3: These registers are available on PIC18C801 only. 2001 Microchip Technology Inc. Advance Information DS39541A-page 57 PIC18C601/801 4.10 Access Bank 4.11 Bank Select Register (BSR) The Access Bank is an architectural enhancement that is very useful for C compiler code optimization. The techniques used by the C compiler are also useful for programs written in assembly. This data memory region can be used for: * * * * * Intermediate computational values Local variables of subroutines Faster context saving/switching of variables Common variables Faster evaluation/control of SFR's (no banking) The need for a large general purpose memory space dictates a RAM banking scheme. When using direct addressing, the BSR should be configured for the desired bank. BSR<3:0> holds the upper 4 bits of the 12-bit RAM address. The BSR<7:4> bits will always read '0's, and writes will have no effect. A MOVLB instruction has been provided in the instruction set to assist in selecting banks. If the currently selected bank is not implemented, any read will return all '0's and all writes are ignored. The STATUS register bits will be set/cleared as appropriate for the instruction performed. Each Bank extends up to 0FFh (256 bytes). All data memory is implemented as static RAM. A MOVFF instruction ignores the BSR, since the 12-bit addresses are embedded into the instruction word. Section 4.12 provides a description of indirect addressing, which allows linear addressing of the entire RAM space. The Access Bank is comprised of the upper 128 bytes in Bank 15 (SFR's) and the lower 128 bytes in Bank 0. These two sections will be referred to as Access Bank High and Access Bank Low, respectively. Figure 4-8 indicates the Access Bank areas. A bit in the instruction word specifies if the operation is to occur in the bank specified by the BSR register, or in the Access Bank. When forced in the Access Bank (a = '0'), the last address in Access Bank Low is followed by the first address in Access Bank High. Access Bank High maps all Special Function Registers so that these registers can be accessed without any software overhead. FIGURE 4-10: DIRECT ADDRESSING Direct Addressing BSR<3:0> 7 from opcode(3) 0 bank select(2) location select(3) 00h 000h 01h 100h 0Eh E00h 0Fh F00h Data Memory(1) 0FFh Bank 0 Note 1: For register file map detail, see Table 4-2. 1FFh Bank 1 EFFh Bank 14 FFFh Bank 15 2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 3: The MOVFF instruction embeds the entire 12-bit address in the instruction. DS39541A-page 58 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 4.12 Indirect Addressing, INDF and FSR Registers If INDF0, INDF1, or INDF2 are read indirectly via an FSR, all '0's are read (zero bit is set). Similarly, if INDF0, INDF1, or INDF2 are written to indirectly, the operation will be equivalent to a NOP instruction and the STATUS bits are not affected. Indirect addressing is a mode of addressing data memory, where the data memory address in the instruction is not fixed. A SFR register is used as a pointer to the data memory location that is to be read or written. Since this pointer is in RAM, the contents can be modified by the program. This can be useful for data tables in the data memory and for software stacks. Figure 4-11 shows the operation of indirect addressing. This shows the moving of the value to the data memory address specified by the value of the FSR register. Indirect addressing is possible by using one of the INDFn (0 n 2) registers. Any instruction using the INDFn register actually accesses the register indicated by the File Select Register, FSRn (0 n 2). Reading the INDFn register itself indirectly (FSRn = '0'), will read 00h. Writing to the INDFn register indirectly, results in a no-operation. The FSRn register contains a 12-bit address, which is shown in Figure 4-11. Example 4-6 shows a simple use of indirect addressing to clear the RAM in Bank 1 (locations 100h-1FFh) in a minimum number of instructions. 4.12.1 INDIRECT ADDRESSING OPERATION Each FSR register has an INDF register associated with it, plus four additional register addresses. Performing an operation on one of these five registers determines how the FSR will be modified during indirect addressing. When data access is done to one of the five INDFn locations, the address selected will configure the FSRn register to: * Do nothing to FSRn after an indirect access (no change) - INDFn * Auto-decrement FSRn after an indirect access (post-decrement) - POSTDECn * Auto-increment FSRn after an indirect access (post-increment) - POSTINCn * Auto-increment FSRn before an indirect access (pre-increment) - PREINCn * Use the value in the WREG register as an offset to FSRn. Do not modify the value of the WREG or the FSRn register after an indirect access (no change) - PLUSWn When using the auto-increment or auto-decrement features, the effect on the FSR is not reflected in the STATUS register. For example, if the indirect address causes the FSR to equal '0', the Z bit will not be set. Incrementing or decrementing an FSR affects all 12 bits. That is, when FSRnL overflows from an increment, FSRnH will be incremented automatically. Adding these features allows the FSRn to be used as a software stack pointer, in addition to its uses for table operations in data memory. Each FSR has an address associated with it that performs an indexed indirect access. When a data access to this INDFn location (PLUSWn) occurs, the FSRn is configured to add the 2's complement value in the WREG register and the value in FSR to form the address before an indirect access. The FSR value is not changed. If an indirect addressing operation is done where the target address is an FSRnH or FSRnL register, the write operation will dominate over the pre- or postincrement/decrement functions. EXAMPLE 4-6: HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING ; ; ; ; ; ; ; Clear INDF register & inc pointer All done with Bank1? NO, clear next LFSR NEXTCLRF FSR0, 100h POSTINC0 BTFSS FSR0H, 1 BRA NEXT CONTINUE; : ; YES, continue There are three indirect addressing registers. To address the entire data memory space (4096 bytes), these registers are 12-bit wide. To store the 12-bits of addressing information, two 8-bit registers are required. These indirect addressing registers are: 1. 2. 3. FSR0: composed of FSR0H:FSR0L FSR1: composed of FSR1H:FSR1L FSR2: composed of FSR2H:FSR2L In addition, there are registers INDF0, INDF1 and INDF2, which are not physically implemented. Reading or writing to these registers activates indirect addressing, with the value in the corresponding FSR register being the address of the data. If an instruction writes a value to INDF0, the value will be written to the address indicated by FSR0H:FSR0L. A read from INDF1 reads the data from the address indicated by FSR1H:FSR1L. INDFn can be used in code anywhere an operand can be used. 2001 Microchip Technology Inc. Advance Information DS39541A-page 59 PIC18C601/801 FIGURE 4-11: INDIRECT ADDRESSING Indirect Addressing 11 8 FSRnH Location Select FSR Register 7 FSRnL 0 0000h Data Memory(1) 0FFFh Note 1: For register file map detail, see Table 4-2. DS39541A-page 60 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 4.13 STATUS Register The STATUS register, shown in Register 4-3, contains the arithmetic status of the ALU. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV, or N bits, then the write to these five bits is disabled. These bits are set or cleared according to the device logic. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear all implemented bits and set the Z bit. This leaves the STATUS register as ---0 0100 (where - = unimplemented). It is recommended, therefore, that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the Z, C, DC, OV, or N bits from the STATUS register. For other instructions which do not affect the status bits, see Table 20-2. Note: The C and DC bits operate as a borrow and digit borrow bit respectively, in subtraction. REGISTER 4-3: STATUS REGISTER U-0 -- bit 7 U-0 -- U-0 -- R/W-x N R/W-x OV R/W-x Z R/W-x DC R/W-x C bit 0 bit 7-5 bit 4 Unimplemented: Read as '0' N: Negative bit This bit is used for signed arithmetic (2's complement). It indicates whether the result of the ALU operation was negative (ALU MSb = 1). 1 = Result was negative 0 = Result was positive OV: Overflow bit This bit is used for signed arithmetic (2's complement). It indicates an overflow of the 7-bit magnitude, which causes the sign bit (bit 7) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit For arithmetic addition and subtraction instructions 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRCF, RRNCF, RLCF, and RLNCF) instructions, this bit is loaded with either the bit 4, or bit 3 of the source register. bit 3 bit 2 bit 1 bit 0 C: Carry/borrow bit For arithmetic addition and subtraction instructions 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRCF, RLCF) instructions, this bit is loaded with either the high, or low order bit of the source register. Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown 2001 Microchip Technology Inc. Advance Information DS39541A-page 61 PIC18C601/801 4.14 RCON Register Note: It is recommended that the POR bit be set after a Power-on Reset has been detected, so that subsequent Power-on Resets may be detected. The Reset Control (RCON) register contains flag bits that allow differentiation between the sources of a device RESET. These flags include the TO, PD, POR and RI bits. This register is readable and writable. REGISTER 4-4: RCON REGISTER R/W-0 IPEN bit 7 U-0 r U-0 -- R/W-1 RI R/W-1 TO R/W-1 PD R/W-0 POR U-0 r bit 0 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (16CXXX compatibility mode) Reserved: Maintain as `0' Unimplemented: Read as '0' RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed 0 = The RESET instruction was executed causing a device RESET (must be set in software after RESET instruction was executed) TO: Watchdog Time-out Flag bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down Detection Flag bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction POR: Power-on Reset Status bit 1 = A Power-on Reset has not occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) Reserved: Maintain as `0' Legend: R = Readable bit - n = Value at POR r = Reserved W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS39541A-page 62 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 5.0 EXTERNAL MEMORY INTERFACE These pins are multiplexed with I/O port pins, but the I/O functions are only enabled when program execution takes place in internal Boot RAM and the EBDIS bit in the MEMCON register is set (see Register 5-1). The External Memory Interface is a feature of the PIC18C601/801 that allows the processor to access external memory devices, such as FLASH, EPROM, SRAM, etc. Memory mapped peripherals may also be accessed. The External Memory Interface physical implementation includes up to 26 pins on the PIC18C601 and up to 38 pins on the PIC18C801. These pins are reserved for external address/data bus functions. 5.1 Memory Control Register (MEMCON) Register 5-1 shows the Memory Control Register (MEMCON). This register contains bits used to control the operation of the External Memory Interface. REGISTER 5-1: MEMCON REGISTER R/W-0 EBDIS bit7 R/W-0 PGRM R/W-0 WAIT1 R/W-0 WAIT0 U-0 -- U-0 -- R/W-0 WM1 R/W-0 WM0 bit0 bit 7 EBDIS: External Bus Disable 1 = External system bus disabled, all external bus drivers are mapped as I/O ports 0 = External system bus enabled, and I/O ports are disabled PGRM: Program RAM Enable 1 = 512 bytes of internal RAM enabled as internal program memory from location 1FFE00h to 1FFFFFh, external program memory at these locations is unused. Internal GPR memory from 400h to 5FFh is disabled and returns 00h. 0 = Internal RAM enabled as internal GPR memory from 400h to 5FFh. Program memory from location 1FFE00h to 1FFFFFh is configured as external program memory. WAIT<1:0>: Table Reads and Writes Bus Cycle Wait Count 11 = Table reads and writes will wait 0 TCY 10 = Table reads and writes will wait 1 TCY 01 = Table reads and writes will wait 2 TCY 00 = Table reads and writes will wait 3 TCY Unimplemented: Read as '0' WM<1:0>: TABLWT Operation with 16-bit Bus 1X = Word Write mode: TABLAT0 and TABLAT1 word output, WRH active when TABLAT1 written 01 = Byte Select mode: TABLAT data copied on both MS and LS Byte, WRH and (UB or LB) will activate 00 = Byte Write mode: TABLAT data copied on both MS and LS Byte, WRH or WRL will activate Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 6 bit 5-4 bit 3-2 bit 1-0 2001 Microchip Technology Inc. Advance Information DS39541A-page 63 PIC18C601/801 5.2 8-bit Mode The External Memory Interface can operate in 8-bit mode. The mode selection is not software configurable, but is programmable via the configuration bits. There are two types of connections in 8-bit mode. They are referred to as: * 8-bit Multiplexed * 8-bit De-Multiplexed Therefore, the designer must choose external memory devices according to timing calculations based on 1/2 Tcy (2 times instruction rate). For proper memory speed selection, glue logic propagation delay times must be considered along with setup and hold times. The Address Latch Enable (ALE) pin indicates that the address bits A<7:0> are available on the External Memory Interface bus. The OE output enable signal will enable one byte of program memory for a portion of the instruction cycle, then BA0 will change and the second byte will be enabled to form the 16-bit instruction word. The least significant bit of the address, BA0, must be connected to the memory devices in this mode. Figure 5-1 shows an example of 8-bit Multiplexed mode on the PIC18C601. The control signals used in 8-bit Multiplexed mode are outlined in Table 5-1. Register 5-2 describes 8-bit Multiplexed mode timing. 5.2.1 8-BIT MULTIPLEXED MODE The 8-bit Multiplexed mode applies only to the PIC18C601. Data and address lines are multiplexed on port pins and must be decoded with glue logic. For 8-bit Multiplexed mode on the PIC18C601, the instructions will be fetched as two 8-bit bytes on a shared data/address bus (PORTD). The two bytes are sequentially fetched within one instruction cycle (TCY). FIGURE 5-1: 8-BIT MULTIPLEXED MODE EXAMPLE D<7:0> A<17:0> AD<7:0> ALE 373 A PIC18C601 CS1 OE WRL Note 1: This signal only applies to Table Writes. See Section 6.0, Table Reads and Writes. TABLE 5-1: Name RG0/ALE RG1/OE 8-BIT MULTIPLEXED MODE CONTROL SIGNALS 8-bit Mux Mode ALE OE WRL BA0 CSIO CS1 Function Address Latch Enable (ALE) control pin Output Enable (OE) control pin Write Low (WRL) control pin Byte address bit 0 Chip Select I/O (See Section 5.4) Chip Select 1 (See Section 5.4) RG2/WRL RG4/BA0 RF3/CSIO RF5/CS1 DS39541A-page 64 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 FIGURE 5-2: 8-BIT MULTIPLEXED MODE TIMING Q1 Q2 Q3 Q4 A16, AD<15:8> ABh 03Ah 55h 0Eh AD<7:0> BA0 ALE OE Opcode Fetch MOVLW 55h from 007556h 5.2.2 8-BIT DE-MULTIPLEXED MODE The 8-bit De-Multiplexed mode applies only to the PIC18C801. Data and address lines are available separately. External components are not necessary in this mode. For 8-bit De-Multiplexed mode on the PIC18C801, the instructions are fetched as two 8-bit bytes on a dedicated data bus (PORTJ). The address will be presented for the entire duration of the fetch cycle on a separate address bus. The two instruction bytes are sequentially fetched within one instruction cycle (TCY). Therefore, the designer must choose external memory devices according to timing calculations, based on 1/2 TCY (2 times instruction rate). For proper memory speed selection, setup and hold times must be considered. The Address Latch Enable (ALE) pin is left unconnected, since glue logic is not necessary. The OE output enable signal will enable one byte of program memory for a portion of the instruction cycle, then BA0 will change and the second byte will be enabled to form the 16-bit instruction word. The least significant bit of the address, BA0, must be connected to the memory devices in this mode. Figure 5-3 shows an example of 8-bit De-Multiplexed mode on the PIC18C801. The control signals used in 8-bit De-Multiplexed mode are outlined in Register 5-2. Register 5-4 describes 8-bit De-Multiplexed mode timing. 2001 Microchip Technology Inc. Advance Information DS39541A-page 65 PIC18C601/801 FIGURE 5-3: 8-BIT DE-MULTIPLEXED MODE EXAMPLE BA0 A<20:0> A<19:16>, AD<15:0> D<7:0> D<7:0> D<7:0> A A0 PIC18C801 ALE CS1 OE WRL CE OE WR(1) Note 1: This signal only applies to Table Writes. See Section 6.0, Table Reads and Writes. TABLE 5-2: Name RG0/ALE RG1/OE RG2/WRL RG4/BA0 RF3/CSIO RF4/CS2 RF5/CS1 8-BIT DE-MULTIPLEXED MODE CONTROL SIGNALS 8-bit De-Mux Mode ALE OE WRL BA0 CSIO CS2 CS1 Function Address Latch Enable (ALE) control pin Output Enable (OE) control pin Write Low (WRL) control pin Byte address bit 0 Chip Select I/O (See Section 5.4) Chip Select 2 (See Section 5.4) Chip Select 1 (See Section 5.4) FIGURE 5-4: 8-BIT DE-MULTIPLEXED MODE TIMING Q1 Q2 Q3 Q4 A16, AD<15:8> 03Ah 55h 0Eh AD<7:0> BA0 ALE OE Opcode Fetch MOVLW 55h from 007556h DS39541A-page 66 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 5.3 16-bit Mode The External Memory Interface can operate in 16-bit mode. The mode selection is not software configurable, but is programmable via the configuration bits. The WM<1:0> bits in the MEMCON register determine three types of connections in 16-bit mode. They are referred to as: * 16-bit Byte Write * 16-bit Word Write * 16-bit Byte Select These three different configurations allow the designer maximum flexibility in using 8-bit and 16-bit memory devices. For all 16-bit modes, the Address Latch Enable (ALE) pin indicates that the address bits A<15:0> are available on the External Memory Interface bus. Following the address latch, the output enable signal (OE ) will enable both bytes of program memory at once to form a 16-bit instruction word. In Byte Select mode, JEDEC standard FLASH memories will require BA0 for the byte address line, and one I/O line, to select between byte and word mode. The other 16-bit modes do not need BA0. JEDEC standard static RAM memories will use the UB or UL signals for byte selection. 5.3.1 16-BIT BYTE WRITE MODE Figure 5-5 shows an example of 16-bit Byte Write mode for the PIC18C601/801. FIGURE 5-5: 16-BIT BYTE WRITE MODE EXAMPLE D<7:0> PIC18C801 AD<15:8> 373 A<19:0> D<15:8> (MSB) A (LSB) A AD<7:0> ALE A<19:16> CS1 OE WRH WRL 373 OE Note 1: This signal only applies to Table Writes. See Section 6.0, Table Reads and Writes. 2001 Microchip Technology Inc. Advance Information DS39541A-page 67 PIC18C601/801 5.3.2 16-BIT WORD WRITE MODE Figure 5-6 shows an example of 16-bit Word Write mode for the PIC18C801. FIGURE 5-6: PIC18C801 16-BIT WORD WRITE MODE EXAMPLE AD<7:0> 373 A<20:1> D<15:0> JEDEC Word EPROM Memory A D<15:0> CE OE WR(1) AD<15:8> 373 ALE A<19:16> CS1 OE WRH Note 1: This signal only applies to Table Writes. See Section 6.0, Table Reads and Writes. 5.3.3 16-BIT BYTE SELECT MODE Figure 5-7 shows an example of 16-bit Byte Select mode for the PIC18C801. FIGURE 5-7: PIC18C801 16-BIT BYTE SELECT MODE EXAMPLE A<20:1> A AD<7:0> 373 JEDEC Word FLASH Memory D<15:0> AD<15:8> 373 ALE A<19:16> OE WRH WRL BA0 I/O CS1 CS2 LB UB A<20:1> A JEDEC Word SRAM Memory D<15:0> CE A0 BYTE/WORD OE WR(1) D<15:0> CE LB UB OE WR(1) D<15:0> Note 1: This signal only applies to Table Writes. See Section 6.0, Table Reads and Writes. DS39541A-page 68 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 5.3.4 16-BIT MODE CONTROL SIGNALS Table 5-3 describes the 16-bit mode control signals for the PIC18C601/801. TABLE 5-3: Name RG0/ALE RG1/OE RG2/WRL RG3/WRH RG4/BA0 RF3/CSIO RF4/CS2 RF5/CS1 RF6/UB RF7/LB I/O PIC18C601/801 16-BIT MODE CONTROL SIGNALS 18C601 16-bit Mode ALE OE WRL WRH BA0 CSIO N/A CS1 UB LB I/O 18C801 16-bit Mode ALE OE WRL WRH BA0 CSIO CS2 CS1 UB LB I/O Function Address Latch Enable (ALE) control pin Output Enable (OE) control pin Write Low (WRL) control pin Write High (WRH) control pin Byte address bit 0 Chip Select I/O (See Section 5.4) Chip Select 2 (See Section 5.4) Chip Select 1 (See Section 5.4) Upper Byte Enable (UB) control pin Lower Byte Enable (LB) control pin I/O as BYTE/WORD control pin for JEDEC FLASH 5.3.5 16-BIT MODE TIMING Figure 5-8 describes the 16-bit mode timing for the PIC18C601/801. FIGURE 5-8: 16-BIT MODE TIMING Q1 Q2 Q3 Q4 A16, AD<15:8> 3AABh 03Ah 0E55h AD<7:0> BA0 ALE OE WRH WRL `1' `1' Opcode Fetch MOVLW 55h from 007556h 2001 Microchip Technology Inc. Advance Information DS39541A-page 69 PIC18C601/801 5.4 Chip Selects Chip select signals are used to select regions of external memory and I/O devices for access. The PIC18C801 has three chip selects and all are programmable. The chip select signals are CS1, CS2 and CSIO. CS1 and CS2 are general purpose chip selects that are used to enable large portions of program memory. CSIO is used to enable external I/O expansion. The PIC18C601uses two of these programmable chip selects: CS1 and CSIO. Two SFRs are used to control the chip select signals. These are CSEL2 and CSELIO (see Register 5-2 and Register 5-3). A chip select signal is asserted low when the CPU makes an access to a dedicated range of addresses specified in the chip select registers, CSEL2 and CSELIO. The 8-bit value found in either of these registers is decoded as one of 256, 8K banks of program memory. If both chip select registers are 00h, all of the chip select signals are disabled and their corresponding pins are configured as I/O. Since the last 512 bytes of program memory are dedicated to internal program RAM, the chip select signals will not activate if the program memory address falls in this range. REGISTER 5-2: CSEL2 REGISTER R/W-1 CSL7 bit 7 R/W-1 CSL6 R/W-1 CSL5 R/W-1 CSL4 R/W-1 CSL3 R/W-1 CSL2 R/W-1 CSL1 R/W-1 CSL0 bit 0 bit 7-0 CSL<7:0>: Chip Select 2 Address Decode bits XXh = All eight bits are compared to the Most Significant bits PC<20:13> of the program counter. If PC<20:13> CSL<7:0> register, then the CS2 signal is low. If PC<20:13> < CSL<7:0>, CS2 is high. 00h = CS2 is inactive Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown REGISTER 5-3: CSELIO REGISTER R/W-1 CSIO7 bit7 R/W-1 CSIO6 R/W-1 CSIO5 R/W-1 CSIO4 R/W-1 CSIO3 R/W-1 CSIO2 R/W-1 CSIO1 R/W-1 CSIO0 bit0 bit 7-0 CSIO<7:0>: Chip Select IO Address Decode bits XXh = All eight bits are compared to the Most Significant bits PC<20:13> of the program counter. If PC<20:13> = CSIO<7:0>, then the CSIO signal is low. If not, CSIO is high. 00h = CSIO is inactive Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown DS39541A-page 70 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 5.4.1 CHIP SELECT 1 (CS1) CS1 is enabled by writing a value other than 00h into either the CSEL2 register, or the CSELIO register. If both of the chip select registers are programmed to 00h, the CS1 signal is not enabled and the RF5 pin is configured as I/O. CS1 is low for all addresses in which CS2 and CSELIO are high. Therefore, if CSEL2 = 20h and CSELIO = 80h, then the CS1 signal will be low for the address that falls between 000000h and (2000h x 20h) - 1 = 03FFFFh. CS1 will always be low for the lower 8K of program memory. Figure 5-9 shows an example address map for CS1. A 00h value in the CSEL2 register will disable the CS2 signal and will configure the RF4 pin as I/O. Figure 5-9 shows an example address map for CS2. 5.4.3 CHIP SELECT I/O (CSIO) CSIO is enabled for a fixed 8K address range starting at the address defined by the 8-bit value contained in CSELIO. If, for instance, the value contained in the CSELIO register is 80h, then the CSIO signal will be low for the address range between 100000h and 101FFFh. If the 8K address block overlaps the address range specified in the CSEL2 register, the CSIO signal will be low, and the CS2 signal will be high, for that region. A 00h value in the CSELIO register will disable the CSIO signal and will configure the RF3 pin as I/O. Figure 5-9 shows an example address map for CSIO. 5.4.2 CHIP SELECT 2 (CS2) CS2 is enabled for program memory accesses, starting at the address derived by the 8-bit value contained in CSEL2. For example, if the value contained in the CSEL2 register is 80h, then the CS2 signal will be asserted low whenever the address is greater than or equal to 2000h x 80h = 100000h. FIGURE 5-9: EXAMPLE CONFIGURATION ADDRESS MAP FOR CS1, CS2, AND CSIO CSEL2 = 80h CSELIO = 00h PROGRAM MEMORY 000000h 000000h CSEL2 = FFh (DEFAULT) CSELIO = FFh (DEFAULT) PROGRAM MEMORY CSEL2 = 20h CSELIO = 80h PROGRAM MEMORY 000000h 03FFFFh 040000h 0FFFFFh 100000h 0FFFFFh 100000h 101FFFh 102000h 1FFDFFh 1FFE00h 1FFFFFh 1FFDFFh 1FFE00h 1FFFFFh 1FFDFFh 1FFE00h 1FFFFFh = CS1 ACTIVE = CS2 ACTIVE = CSIO ACTIVE = NO CHIP SELECT ACTIVE INTERNAL EXECUTION IF PGRM = 1 2001 Microchip Technology Inc. Advance Information DS39541A-page 71 PIC18C601/801 5.5 External Wait Cycles The external memory interface supports wait cycles. Wait cycles only apply to Table Read and Table Write operations over the external bus. See Section 6.0 for more details. Since the device execution is tied to instruction fetches, there is no need to execute faster than the fetch rate. So, if the program needs to be slowed, the processor speed must be slowed with a different TCY time. DS39541A-page 72 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 6.0 TABLE READS/TABLE WRITES PIC18C601/801 devices use two memory spaces: the external program memory space and the data memory space. Table Reads and Table Writes have been provided to move data between these two memory spaces through an 8-bit register (TABLAT). The operations that allow the processor to move data between the data and external program memory spaces are: * Table Read (TBLRD) * Table Write (TBLWT) Table Read operations retrieve data from external program memory and place it into the data memory space. Figure 6-1 shows the operation of a Table Read with program and data memory. Table Write operations store data from the data memory space into external program memory. Figure 6-2 shows the operation of a Table Write with external program and data memory. Table operations work with byte entities. A table block containing data is not required to be word aligned, so a table block can start and end at any byte address. If a Table Write is being used to write an executable program to program memory, program instructions must be word aligned. FIGURE 6-1: TABLE READ OPERATION Table Pointer(1) TBLPTRU TBLPTRH TBLPTRL Table Latch (8-bit) TABLAT External Program Memory Instruction: TBLRD* Program Memory (TBLPTR) Note 1: Table Pointer points to a byte in external program memory. FIGURE 6-2: TABLE WRITE OPERATION Table Pointer(1) TBLPTRU TBLPTRH TBLPTRL Table Latch (8-bit) TABLAT External Program Memory Instruction: TBLWT* External Program Memory (TBLPTR) Note 1: Table Pointer points to a byte in external program memory. 2001 Microchip Technology Inc. Advance Information DS39541A-page 73 PIC18C601/801 6.1 Control Registers 6.1.2 Several control registers are used in conjunction with the TBLRD and TBLWT instructions. These include: * TABLAT register * TBLPTR registers TBLPTR - TABLE POINTER REGISTER 6.1.1 TABLAT - TABLE LATCH REGISTER The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch is used to hold 8-bit data during data transfers between program memory and data memory. The Table Pointer (TBLPTR) addresses a byte within the program memory. The TBLPTR is comprised of three SFR registers (Table Pointer Upper byte, High byte and Low byte). These three registers (TBLPTRU:TBLPTRH:TBLPTRL) join to form a 21-bit wide pointer. The 21-bits allow the device to address up to 2 Mbytes of program memory space. The table pointer TBLPTR is used by the TBLRD and TBLWRT instructions. These instructions can update the TBLPTR in one of four ways, based on the table operation. These operations are shown in Table 6-1. These operations on the TBLPTR only affect the low order 21-bits. TABLE 6-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write Example TBLRD* TBLWT* TBLRD*+ TBLWT*+ TBLRD*TBLWT*TBLRD+* TBLWT+* DS39541A-page 74 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 6.2 Table Read The TBLRD instruction is used to retrieve data from external program memory and place it into data memory. TBLPTR points to a byte address in external program memory space. Executing TBLRD places the byte into TABLAT. In addition, TBLPTR can be modified automatically for the next Table Read operation. Table Reads from external program memory are performed one byte at a time. If the external interface is 8-bit, the bus interface circuitry in TABLAT will load the external value into TABLAT. If the external interface is 16-bit, interface circuitry in TABLAT will select either the high or low byte of the data from the 16-bit bus, based on the least significant bit of the address. Example 6-1describes how to use TBLRD. Figure 6-3 and Figure 6-4 show Table Read timings for an 8-bit external interface, and Figure 6-5 describes Table Read timing for a 16-bit interface. EXAMPLE 6-1: ; Read CLRF CLRF MOVLW MOVWF TBLRD* TABLE READ CODE EXAMPLE a byte from location 0020h TBLPTRU ; clear upper 5 bits of TBLPTR TBLPTRH ; clear higher 8 bits of TBLPTR 20h ; Load 20h into TBLPTRL ; TBLPTRL ; Data is in TABLAT FIGURE 6-3: Q1 TBLRD EXTERNAL INTERFACE TIMING (8-BIT MULTIPLEXED MODE) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 A<15:8> 03Ah 03Ah CCFh 03Ah AD<7:0> AAh 08h 00h ABh 55h 0Eh 33h 92h ACh 55h 0Fh BA0 ALE OE '1' WRH '1' '1' WRL '1' Memory Cycle Instruction Execution Opcode Fetch TBLRD* from 007554h INST(PC-2) Opcode Fetch MOVLW 55h from 007556h TBLRD Cycle1 TABLRD 92h from 199E67h Opcode Fetch ADDLW 55h from 007558h MOVLW TBLRD Cycle2 2001 Microchip Technology Inc. Advance Information DS39541A-page 75 PIC18C601/801 FIGURE 6-4: Q1 TBLRD EXTERNAL INTERFACE TIMING (8-BIT DE-MULTIPLEXED MODE) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 A<15:8> 03AAAh 03AABh CCF33h 03AACh AD<7:0> 08h 00h 55h 0Eh 92h 55h BA0 ALE OE '1' WRH '1' WRL Memory Cycle Instruction Execution Opcode Fetch TBLRD* from 007554h INST(PC-2) Opcode Fetch MOVLW 55h from 007556h TBLRD Cycle1 TABLRD 92h from 199E67h Opcode Fetch ADDLW 55h from 007558h MOVLW '1' '1' TBLRD Cycle2 FIGURE 6-5: Q1 TBLRD EXTERNAL BUS TIMING (16-BIT MODE) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 A<19:16> 0h 0h Ch 0E55h 0h 0F55h AD<15:0> 3AAAh 0008h 3AABh CF33h 9256h 3AACh BA0 ALE OE '1' WRH '1' WRL Memory Cycle Instruction Execution Opcode Fetch TBLRD* from 007554h INST(PC-2) Opcode Fetch MOVLW 55h from 007556h TBLRD Cycle1 TABLRD 92h from 199E67h Opcode Fetch ADDLW 55h from 007558h MOVLW '1' '1' TBLRD Cycle2 DS39541A-page 76 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 6.3 Table Write Table Write operations store data from the data memory space into external program memory. PIC18C601/801devices perform Table Writes one byte at a time. Table Writes to external memory are two-cycle instructions, unless wait states are enabled. The last cycle writes the data to the external memory location. 16-bit interface Table Writes depend on the type of external device that is connected and the WM<1:0> bits in the MEMCON register (See Figure 5-2). Example 6-2 describes how to use TBLWT. EXAMPLE 6-2: ; Write CLRF CLRF MOVLW MOVWF MOVLW MOVWF TBLWT* TABLE WRITE CODE EXAMPLE a byte to location 0020h TBLPTRU ; clear upper 5 bits of TBLPTR TBLPTRH ; clear higher 8 bits of TBLPTR 20h ; Load 20h into TBLPTRL ; TBLPTRL 55h ; Load 55h into TBLAT ; TBLAT ; Write it 2001 Microchip Technology Inc. Advance Information DS39541A-page 77 PIC18C601/801 6.3.1 8-BIT EXTERNAL TABLE WRITES When the external bus is 8-bit, the byte-wide Table Write exactly corresponds to the bus length and there are no special considerations required. The WRL signal is used as the active write signal. Figure 6-6 and Figure 6-7 show the timings associated with the 8-bit modes. FIGURE 6-6: Q1 TBLWT EXTERNAL INTERACE TIMING (8-BIT MULTIPLEXED MODE) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 A<19:8> 03Ah 03Ah CCFh 03Ah AD<7:0> AAh 08h 00h ABh 55h 0Eh 33h 92h ACh 55h 0Fh BA0 ALE OE WRH '1' WRL Memory Cycle Instruction Execution Opcode Fetch TBLWT* from 007554h INST(PC-2) Opcode Fetch MOVLW 55h from 007556h TBLWT Cycle1 TBLWT 92h to 199E67h Opcode Fetch ADDLW 55h from 007558h MOVLW TBLWT Cycle2 DS39541A-page 78 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 FIGURE 6-7: Q1 TBLWT EXTERNAL INTERFACE TIMING (8-BIT DE-MULTIPLEXED MODE) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 A<19:8> 03Ah 03Ah CCFh 03Ah AD<7:0> 08h 00h 55h 0Eh 92h 55h 0Fh BA0 ALE OE WRH '1' WRL Memory Cycle Instruction Execution Opcode Fetch TBLWT* from 007554h INST(PC-2) Opcode Fetch MOVLW 55h from 007556h TBLWT Cycle1 TBLWT 92h to 199E67h Opcode Fetch ADDLW 55h from 007558h MOVLW TBLWT Cycle2 2001 Microchip Technology Inc. Advance Information DS39541A-page 79 PIC18C601/801 6.3.2 16-BIT EXTERNAL TABLE WRITE (BYTE WRITE MODE) This mode allows Table Writes to byte-wide external memories. During a TBLWT cycle, the TABLAT data is presented on the upper and lower byte of the AD<15:0> bus. The appropriate WRH or WRL line is strobed based on the LSb of the TBLPTR. Figure 6-8 shows the timing associated with this mode. FIGURE 6-8: TBLWT EXTERNAL INTERFACE TIMING (16-BIT BYTE WRITE MODE) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 A<19:16> 0h 0h Ch 0h 0h Ch AD<15:0> 3AAAh 000Dh 3AABh 6FF4h CF33h 5656h 3AACh 000Ch 3AADh 0E55h CF33h 9292h BA0 ALE OE WRH WRL UB LB Opcode Fetch TBLWT*+ from 007554h INST(PC-2) Opcode Fetch MOVWF TABLAT from 007556h TBLWT*+ Cycle1 TBLWT 56h to 199E66h TBLWT*+ Cycle2 Opcode Fetch TBLWT* from 007558h MOVWF Opcode Fetch MOVLW 55h from 00755Ah TBLWT* Cycle1 TBLWT 92h to 199E67h TBLWT* Cycle2 Memory Cycle Instruction Execution DS39541A-page 80 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 6.3.3 EXTERNAL TABLE WRITE IN 16-BIT WORD WRITE MODE During a TBLWT cycle to an odd address, where TBLPTR<0> = 1, the TABLAT data is presented on the upper byte of the AD<15:0> bus. The contents of the holding latch are presented on the lower byte of the AD<15:0> bus. The WRH line is strobed for each write cycle and the WRL line is unused. The BA0 line indicates the LSb of TBLPTR, but it is unnecessary. The UB and LB lines are active to select both bytes. The obvious limitation to this method is that the TBLWT must be done in pairs on a specific word boundary to correctly write a word location. Figure 6-9 shows the timing associated with this mode. This mode allows Table Writes to any type of wordwide external memories. This method makes a distinction between TBLWT cycles to even or odd addresses. During a TBLWT cycle to an even address, where TBLPTR<0> = 0, the TABLAT data is transferred to a holding latch and the external address data bus is tristated for the data portion of the bus cycle. No write signals are activated. FIGURE 6-9: TBLWT EXTERNAL INTERFACE TIMING (16-BIT WORD WRITE MODE) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 A<19:16> 0h 0h Ch 0h 0h Ch AD<15:0> 3AAAh 000Dh 3AABh 6FF4h CF33h 3AACh 000Ch 3AADh 0E55h CF33h 9256h BA0 ALE OE WRH WRL '1' UB LB Memory Cycle Instruction Execution Opcode Fetch TBLWT*+ from 007554h INST(PC-2) Opcode Fetch MOVWF TABLAT from 007556h TBLWT 56h to 199E66h Opcode Fetch TBLWT* from 007558h MOVWF Opcode Fetch MOVLW 55h from 00755Ah TBLWT* Cycle1 TBLWT 92h to 199E67h TBLWT* Cycle2 TBLWT*+ Cycle1 TBLWT*+ Cycle2 2001 Microchip Technology Inc. Advance Information DS39541A-page 81 PIC18C601/801 6.3.4 16-BIT EXTERNAL TABLE WRITE (BYTE SELECT MODE) WRL line is unused. The BA0 or UB or UL lines are used to select the byte to be written, based on the LSb of the TBLPTR. JEDEC standard flash memories will require a I/O port line to become a BYTE/WORD input signal and will use the BA0 signal as a byte address. JEDEC standard static RAM memories will use the UB or UL signals to select the byte. Figure 6-10 shows the timing associated with this mode. This mode allows Table Writes to word-wide external memories that have byte selection capabilities. This generally includes word-wide FLASH devices and word-wide static RAM devices. During a TBLWT cycle, the TABLAT data is presented on the upper and lower byte of the AD<15:0> bus. The WRH line is strobed for each write cycle and the FIGURE 6-10: TBLWT EXTERNAL INTERFACE TIMING (16-BIT BYTE SELECT MODE) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 A<19:16> 0h 0h Ch 0h 0h Ch AD<15:0> 3AAAh 000Dh 3AABh 6FF4h CF33h 5656h 3AACh 000Ch 3AADh 0E55h CF33h 9292h BA0 ALE OE WRH WRL '1' UB LB Memory Cycle Instruction Execution Opcode Fetch TBLWT*+ from 007554h INST(PC-2) Opcode Fetch MOVWF TABLAT from 007556h TBLWT 56h to 199E66h Opcode Fetch TBLWT* from 007558h MOVWF Opcode Fetch MOVLW 55h from 00755Ah TBLWT* Cycle1 TBLWT 92h to 199E67h TBLWT* Cycle2 TBLWT*+ Cycle1 TBLWT*+ Cycle2 DS39541A-page 82 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 6.4 Long Writes Long writes will not be supported on the PIC18C601/801 to program FLASH configuration memory. The configuration locations can only be programmed in ICSP mode. The WAIT<1:0> bits in the MEMCON register will select 0, 1, 2, or 3 extra TCY cycles per TBLRD/TBWLT cycle. The wait will occur on Q4. The default setting of the wait on power-up is to assert a maximum wait of 3TCY cycles. This insures that slow memories will work in Microprocessor mode immediately after RESET. Figure 6-11 shows 8-bit external bus timing for a Table Read with 2 wait cycles. Figure 6-12 shows 16-bit external bus timing for a Table Read with 1 wait cycle. 6.5 External Wait Cycles The Table Reads and Writes have the capability to insert wait states when accessing external memory. These wait states only apply to the execution of a Table Read or Write to external memory and not to instruction fetches out of external memory. The guidelines presented in Section 5.0 must be followed to select the proper memory speed grade for the device operating frequency. FIGURE 6-11: Apparent Q Actual Q EXTERNAL INTERFACE TIMING (8-BIT MODE) Q1 Q2 Q1 Q2 Q3 Q3 Q4 Q4 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Q4 Q1 Q4 Q2 Q4 Q3 Q4 Q4 Q4 Q1 Q4 Q2 Q4 Q3 Q4 Q4 A<19:8> 03Ah CCFh AD<7:0> ABh 55h 0Eh 33h 92h BA0 ALE OE 2TCY Wait Opcode Fetch MOVLW 55h from 007556h Table Read of 92h from 199E67h 2001 Microchip Technology Inc. Advance Information DS39541A-page 83 PIC18C601/801 FIGURE 6-12: Apparent Q Actual Q A<19:16> EXTERNAL INTERFACE TIMING (16-BIT MODE) Q1 Q1 Q2 Q2 0h Q3 Q3 Q4 Q4 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Q4 Q1 0Ch Q4 Q2 Q4 Q3 Q4 Q4 AD<15:0> 3AABh 0E55h CF33h 9256h BA0 ALE OE WRH WRL '1' '1' 1TCY Wait Opcode Fetch MOVLW 55h from 007556h Table Read of 92h from 199E67h '1' '1' DS39541A-page 84 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 7.0 8 X 8 HARDWARE MULTIPLIER An 8 x 8 hardware multiplier is included in the ALU of PIC18C601/801 devices. By making the multiply a hardware operation, it completes in a single instruction cycle. This is an unsigned multiply that gives a 16-bit result. The result is stored into the 16-bit product register pair (PRODH:PRODL). The multiplier does not affect any flags in the STATUS register. Making the 8 x 8 multiplier execute in a single cycle gives the following advantages: * Higher computational throughput * Reduces code size requirements for multiply algorithms The performance increase allows the device to be used in some applications previously reserved for Digital Signal Processors. Table 7-1 shows a performance comparison between enhanced devices using the single cycle hardware multiply, and performing the same function without the hardware multiply. TABLE 7-1: Routine PERFORMANCE COMPARISON Multiply Method Without hardware multiply Hardware multiply Without hardware multiply Hardware multiply Without hardware multiply Hardware multiply Without hardware multiply Hardware multiply Program Memory (Words) 13 1 33 6 21 24 52 36 Cycles (Max) 69 1 91 6 242 24 254 36 Time @ 25 MHz 11.0 s 160.0 ns 14.6 s 960.0 ns 38.7 s 3.8 s 40.6 s 5.8 s @ 10 MHz 27.6 s 400.0 ns 36.4 s 2.4 s 96.8 s 9.6 s 102.6 s 14.4 s @ 4 MHz 69.0 s 1.0 s 91.0 s 6.0 s 242.0 s 24.0 s 254.0 s 36.0 s 8 x 8 unsigned 8 x 8 signed 16 x 16 unsigned 16 x 16 signed 2001 Microchip Technology Inc. Advance Information DS39541A-page 85 PIC18C601/801 7.1 Operation EXAMPLE 7-3: MOVFF MULWF MOVFF MOVFF ; MOVFF MULWF MOVFF MOVFF ; MOVFF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ; MOVFF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ARG1H, WREG ARG2L PRODL, W RES1 PRODH, W RES2 WREG RES3 ; ; ; ; ; ; ; ; ; ARG1H * ARG2L -> PRODH:PRODL Add cross products ARG1L, WREG ARG2H PRODL, W RES1 PRODH, W RES2 WREG RES3 ; ; ; ; ; ; ; ; ARG1L * ARG2H -> PRODH:PRODL Add cross products ARG1H, WREG ARG2H PRODH, RES3 PRODL, RES2 ; ARG1H * ARG2H -> ; PRODH:PRODL ; ; Example 7-1 shows the sequence to perform an 8 x 8 unsigned multiply. Only one instruction is required when one argument of the multiply is already loaded in the WREG register. Example 7-2 shows the sequence to do an 8 x 8 signed multiply. To account for the sign bits of the arguments, each argument's most significant bit (MSb) is tested and the appropriate subtractions are done. 16 x 16 UNSIGNED MULTIPLY ROUTINE ; ARG1L * ARG2L -> ; PRODH:PRODL ; ; ARG1L, WREG ARG2L PRODH, RES1 PRODL, RES0 EXAMPLE 7-1: MOVFF MULWF 8 x 8 UNSIGNED MULTIPLY ROUTINE ; ; ARG1 * ARG2 -> ; PRODH:PRODL ARG1, WREG ARG2 EXAMPLE 7-2: MOVFF MULWF BTFSC SUBWF MOVFF BTFSC SUBWF 8 x 8 SIGNED MULTIPLY ROUTINE ; ; ; ; ; ARG1 * ARG2 -> PRODH:PRODL Test Sign Bit PRODH = PRODH - ARG1 ARG1, WREG ARG2 ARG2, SB PRODH ARG2, WREG ARG1, SB PRODH ; Test Sign Bit ; PRODH = PRODH ; - ARG2 Example 7-3 shows the sequence to perform a 16 x 16 unsigned multiply. Equation 7-1 shows the algorithm that is used. The 32-bit result is stored in 4 registers RES3:RES0. Example 7-4 shows the sequence to perform a 16 x 16 signed multiply. Equation 7-2 shows the algorithm used. The 32-bit result is stored in four registers, RES3:RES0. To account for the sign bits of the arguments, each argument pairs' most significant bit (MSb) is tested and the appropriate subtractions are done. EQUATION 7-1: 16 x 16 UNSIGNED MULTIPLICATION ALGORITHM ARG1H:ARG1L * ARG2H:ARG2L (ARG1H * ARG2H * 216)+ (ARG1H * ARG2L * 28)+ (ARG1L * ARG2H * 28)+ (ARG1L * ARG2L) EQUATION 7-2: 16 x 16 SIGNED MULTIPLICATION ALGORITHM RES3:RES0 = = RES3:RES0 = ARG1H:ARG1L * ARG2H:ARG2L + = (ARG1H * ARG2H * 216) + (ARG1H * ARG2L * 28) (ARG1L * ARG2H * 28) + + (ARG1L * ARG2L) (-1 * ARG2H<7> * ARG1H:ARG1L * 216) (-1 * ARG1H<7> * ARG2H:ARG2L * 216) + DS39541A-page 86 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 EXAMPLE 7-4: MOVFF MULWF MOVFF MOVFF ; MOVFF MULWF MOVFF MOVFF ; MOVFF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ; MOVFF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ; BTFSS GOTO MOVFF SUBWF MOVFF SUBWFB ; SIGN_ARG1 BTFSS GOTO MOVFF SUBWF MOVFF SUBWFB ; CONT_CODE : ARG2H, 7 SIGN_ARG1 ARG1L, WREG RES2 ARG1H, WREG RES3 ; ARG2H:ARG2L neg? ; no, check ARG1 ; ; ; ARG1H, WREG ARG2L PRODL, W RES1 PRODH, W RES2 WREG RES3 ; ; ARG1H * ARG2L -> ; PRODH:PRODL ; ; Add cross ; products ; ; ; ARG1L, WREG ARG2H PRODL, W RES1 PRODH, W RES2 WREG RES3 ; ARG1L * ARG2H -> ; PRODH:PRODL ; ; Add cross ; products ; ; ; ARG1H, WREG ARG2H PRODH, RES3 PRODL, RES2 ; ARG1H * ARG2H -> ; PRODH:PRODL ; ; 16 x 16 SIGNED MULTIPLY ROUTINE ; ARG1L * ARG2L -> ; PRODH:PRODL ; ; ARG1L, WREG ARG2L PRODH, RES1 PRODL, RES0 ARG1H, 7 CONT_CODE ARG2L, WREG RES2 ARG2H, WREG RES3 ; ARG1H:ARG1L neg? ; no, done ; ; ; 2001 Microchip Technology Inc. Advance Information DS39541A-page 87 PIC18C601/801 NOTES: DS39541A-page 88 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 8.0 INTERRUPTS PIC18C601/801 devices have 15 interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high priority level, or a low priority level. The high priority interrupt vector is at 000008h and the low priority interrupt vector is at 000018h. High priority interrupt events will override any low priority interrupts that may be in progress. There are 10 registers that are used to control interrupt operation. These registers are: * * * * * * * RCON INTCON INTCON2 INTCON3 PIR1, PIR2 PIE1, PIE2 IPR1, IPR2 When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with PICmicro(R) mid-range devices. In Compatibility mode, the interrupt priority bits for each source have no effect. The PEIE bit (INTCON register) enables/disables all peripheral interrupt sources. The GIE bit (INTCON register) enables/disables all interrupt sources. All interrupts branch to address 000008h in Compatibility mode. When an interrupt is responded to, the Global Interrupt Enable bit is cleared to disable further interrupts. If the IPEN bit is cleared, this is the GIE bit. If interrupt priority levels are used, this will be either the GIEH or GIEL bit. High priority interrupt sources can interrupt a low priority interrupt. The return address is pushed onto the stack and the PC is loaded with the interrupt vector address (000008h or 000018h). Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bits must be cleared in software before re-enabling interrupts, to avoid recursive interrupts. The "return from interrupt" instruction, RETFIE, exits the interrupt routine and sets the GIE bit (GIEH or GIEL if priority levels are used), which re-enables interrupts. For external interrupt events, such as the INT pins or the PORTB input change interrupt, the interrupt latency will be three to four instruction cycles. The exact latency is the same for one or two cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding enable bit or the GIE bit. It is recommended that the Microchip header files supplied with MPLAB(R) IDE be used for the symbolic bit names in these registers. This allows the assembler/ compiler to automatically take care of the placement of these bits within the specified register. Each interrupt source has three bits to control its operation. The functions of these bits are: * Flag bit to indicate that an interrupt event occurred * Enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set * Priority bit to select high priority or low priority The interrupt priority feature is enabled by setting the IPEN bit (RCON register). When interrupt priority is enabled, there are two bits that enable interrupts globally. Setting the GIEH bit (INTCON register) enables all interrupts that have the priority bit set. Setting the GIEL bit (INTCON register) enables all interrupts that have the priority bit cleared. When the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 000008h or 000018h, depending on the priority level. Individual interrupts can be disabled through their corresponding enable bits. 2001 Microchip Technology Inc. Advance Information DS39541A-page 89 PIC18C601/801 FIGURE 8-1: INTERRUPT LOGIC TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0F INT0E INT1F INT1E INT1P INT2F INT2E INT2P Wake-up if in SLEEP mode Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit Interrupt to CPU Vector to location 0008h GIEH/GIE TMR1IF TMR1IE TMR1IP XXXXIF XXXXIE XXXXIP Additional Peripheral Interrupts High Priority Interrupt Generation Low Priority Interrupt Generation IPEN IPEN GIEL/PEIE IPEN Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0F INT0E Additional Peripheral Interrupts INT1F INT1E INT1P INT2F INT2E INT2P Interrupt to CPU Vector to Location 0018h TMR1IF TMR1IE TMR1IP XXXXIF XXXXIE XXXXIP GIEL\PEIE DS39541A-page 90 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 8.1 Control Registers 8.1.1 INTCON REGISTERS This section contains the control and status registers. The INTCON Registers are readable and writable registers, which contain various enable, priority, and flag bits. REGISTER 8-1: INTCON REGISTER R/W-0 bit 7 R/W-0 R/W-0 TMR0IE R/W-0 INT0IE R/W-0 RBIE R/W-0 TMR0IF R/W-0 INT0IF R/W-x RBIF bit 0 GIE/GIEH PEIE/GIEL bit 7 GIE/GIEH: Global Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts When IPEN = 1: 1 = Enables all high priority interrupts 0 = Disables all high priority interrupts PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1: 1 = Enables all low priority peripheral interrupts 0 = Disables all priority peripheral interrupts TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software) 0 = The INT0 external interrupt did not occur RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows software polling. 2001 Microchip Technology Inc. Advance Information DS39541A-page 91 PIC18C601/801 REGISTER 8-2: INTCON2 REGISTER R/W-1 RBPU bit 7 bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge INTEDG2: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge Unimplemented: Read as '0' TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Unimplemented: Read as '0' RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-1 INTEDG0 R/W-1 INTEDG1 R/W-1 INTEDG2 U-0 -- R/W-1 TMR0IP U-0 -- R/W-1 RBIP bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows software polling. DS39541A-page 92 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 REGISTER 8-3: INTCON3 REGISTER R/W-1 INT2IP bit 7 bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority Unimplemented: Read as '0' INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt Unimplemented: Read as '0' INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-1 INT1IP U-0 -- R/W-0 INT2IE R/W-0 INT1IE U-0 -- R/W-0 INT2IF R/W-0 INT1IF bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows software polling. 2001 Microchip Technology Inc. Advance Information DS39541A-page 93 PIC18C601/801 8.1.2 PIR REGISTERS 8.1.3 PIE REGISTERS The Peripheral Interrupt Request (PIR) registers contain the individual flag bits for the peripheral interrupts (Register 8-5). There are two Peripheral Interrupt Request (Flag) registers (PIR1, PIR2). Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit, GIE (INTCON register). 2: User software should ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt, and after servicing that interrupt. The Peripheral Interrupt Enable (PIE) registers contain the individual enable bits for the peripheral interrupts (Register 8-6). There are two two Peripheral Interrupt Enable registers (PIE1, PIE2). When IPEN is clear, the PEIE bit must be set to enable any of these peripheral interrupts. 8.1.4 IPR REGISTERS The Interrupt Priority (IPR) registers contain the individual priority bits for the peripheral interrupts (Register 8-9). There are two Peripheral Interrupt Priority registers (IPR1, IPR2). The operation of the priority bits requires that the Interrupt Priority Enable bit (IPEN) be set. 8.1.5 RCON REGISTER The Reset Control (RCON) register contains the bit that is used to enable prioritized interrupts (IPEN). REGISTER 8-4: RCON REGISTER R/W-0 IPEN bit 7 U-0 r U-0 -- R/W-1 RI R/W-1 TO R/W-1 PD R/W-0 POR U-0 r bit 0 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (16CXXX compatibility mode) Reserved: Maintain as '0' Unimplemented: Read as '0' RI: RESET Instruction Flag bit For details of bit operation, see Register 4-4 TO: Watchdog Time-out Flag bit For details of bit operation, see Register 4-4 PD: Power-down Detection Flag bit For details of bit operation, see Register 4-4 POR: Power-on Reset Status bit For details of bit operation, see Register 4-4 Reserved: Maintain as '0' Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS39541A-page 94 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 REGISTER 8-5: PIR1 REGISTER U-0 -- bit 7 bit 7 bit 6 Unimplemented: Read as '0' ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer, RCREG, is full (cleared when RCREG is read) 0 = The USART receive buffer is empty TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer, TXREG, is empty (cleared when TXREG is written) 0 = The USART transmit buffer is full SSPIF: Master Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow R/W-0 ADIF R-0 RCIF R-0 TXIF R/W-0 SSPIF R/W-0 CCP1IF R/W-0 TMR2IF R/W-0 TMR1IF bit 0 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown 2001 Microchip Technology Inc. Advance Information DS39541A-page 95 PIC18C601/801 REGISTER 8-6: PIR2 REGISTER U-0 -- bit 7 bit 7-4 bit 3 Unimplemented: Read as'0' BCLIF: Bus Collision Interrupt Flag bit 1 = A bus collision occurred (must be cleared in software) 0 = No bus collision occurred LVDIF: Low Voltage Detect Interrupt Flag bit 1 = A low voltage condition occurred (must be cleared in software) 0 = The device voltage is above the Low Voltage Detect trip point TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software) 0 = TMR3 register did not overflow CCP2IF: CCPx Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- R/W-0 BCLIF R/W-0 LVDIF R/W-0 TMR3IF R/W-0 CCP2IF bit 0 bit 2 bit 1 bit 0 DS39541A-page 96 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 REGISTER 8-7: PIE1 REGISTER U-0 -- bit 7 bit 7 bit 6 Unimplemented: Read as '0' ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt SSPIE: Master Synchronous Serial Port Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt R/W-0 ADIE R/W-0 RCIE R/W-0 TXIE R/W-0 SSPIE R/W-0 CCP1IE R/W-0 TMR2IE R/W-0 TMR1IE bit 0 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown 2001 Microchip Technology Inc. Advance Information DS39541A-page 97 PIC18C601/801 REGISTER 8-8: PIE2 REGISTER U-0 -- bit 7 bit 7-4 bit 3 Unimplemented: Read as '0' BCLIE: Bus Collision Interrupt Enable bit 1 = Enabled 0 = Disabled LVDIE: Low Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enables the TMR3 overflow interrupt 0 = Disables the TMR3 overflow interrupt CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- R/W-0 BCLIE R/W-0 LVDIE R/W-0 TMR3IE R/W-0 CCP2IE bit 0 bit 2 bit 1 bit 0 DS39541A-page 98 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 REGISTER 8-9: IPR1 REGISTER U-0 -- bit 7 bit 7 bit 6 Unimplemented: Read as '0' ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority RCIP: USART Receive Interrupt Priority bit 1 = High priority 0 = Low priority TXIP: USART Transmit Interrupt Priority bit 1 = High priority 0 = Low priority SSPIP: Master Synchronous Serial Port Interrupt Priority bit 1 = High priority 0 = Low priority CCP1IP: CCP1 Interrupt Priority bit 1 = High priority 0 = Low priority TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority R/W-1 ADIP R/W-1 RCIP R/W-1 TXIP R/W-1 SSPIP R/W-1 CCP1IP R/W-1 TMR2IP R/W-1 TMR1IP bit 0 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown 2001 Microchip Technology Inc. Advance Information DS39541A-page 99 PIC18C601/801 REGISTER 8-10: IPR2 REGISTER U-0 -- bit 7 bit 7-4 bit 3 Unimplemented: Read as '0' BCLIP: Bus Collision Interrupt Priority bit 1 = High priority 0 = Low priority LVDIP: Low Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- R/W-1 BCLIP R/W-1 LVDIP R/W-1 TMR3IP R/W-1 CCP2IP bit 0 bit 2 bit 1 bit 0 DS39541A-page 100 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 8.1.6 INT INTERRUPTS External interrupts on the RB0/INT0, RB1/INT1 and RB2/INT2 pins are edge triggered: either rising, if the corresponding INTEDGx bit is set in the INTCON2 register, or falling, if the INTEDGx bit is clear. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit INTxIF is set. This interrupt can be disabled by clearing the corresponding enable bit INTxIE. Flag bit INTxIF must be cleared in software in the Interrupt Service Routine before re-enabling the interrupt. All external interrupts (INT0, INT1 and INT2) can wake-up the processor from SLEEP, if bit INTxIE was set prior to going into SLEEP. If the global interrupt enable bit GIE is set, the processor will branch to the interrupt vector following wake-up. Interrupt priority for INT1 and INT2 is determined by the value contained in the interrupt priority bits INT1IP (INTCON3 register) and INT2IP (INTCON3 register). There is no priority bit associated with INT0; it is always a high priority interrupt source. in the TMR0H:TMR0L registers will set flag bit TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit TMR0IE (INTCON register). Interrupt priority for Timer0 is determined by the value contained in the interrupt priority bit TMR0IP (INTCON2 register). See Section 10.0 for further details on the Timer0 module. 8.1.8 PORTB INTERRUPT-ON-CHANGE An input change on PORTB<7:4> sets flag bit RBIF (INTCON register). The interrupt can be enabled/ disabled by setting/clearing enable bit RBIE (INTCON register). Interrupt priority for PORTB interrupt-onchange is determined by the value contained in the interrupt priority bit RBIP (INTCON2 register). 8.2 Context Saving During Interrupts 8.1.7 TMR0 INTERRUPT In 8-bit mode (which is the default), an overflow (0FFh 00h) in the TMR0 register will set flag bit TMR0IF. In 16-bit mode, an overflow (0FFFFh 0000h) During an interrupt, the return PC value is saved on the stack. Additionally, the WREG, STATUS and BSR registers are saved on the fast return stack. If a fast return from interrupt is not used (See Section 4.3), the user may need to save the WREG, STATUS and BSR registers in software. Depending on the user's application, other registers may also need to be saved. Example 8-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. EXAMPLE 8-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM ; W_TEMP is in Low Access bank ; STATUS_TEMP located anywhere ; BSR located anywhere MOVWF W_TEMP MOVFF STATUS, STATUS_TEMP MOVFF BSR, BSR_TEMP ; ; USER ISR CODE ; MOVFF BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS ; Restore BSR ; Restore WREG ; Restore STATUS 2001 Microchip Technology Inc. Advance Information DS39541A-page 101 PIC18C601/801 NOTES: DS39541A-page 102 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 9.0 I/O PORTS EXAMPLE 9-1: CLRF PORTA ; ; ; ; ; ; ; ; ; ; ; ; ; INITIALIZING PORTA Initialize PORTA by clearing output data latches Alternate method to clear output data latches Configure A/D for digital inputs Value used to initialize data direction Set RA3:RA0 as inputs RA5:RA4 as outputs Depending on the device selected, there are up to 9 ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation. These registers are: * TRIS register (data direction register) * PORT register (reads the levels on the pins of the device) * LAT register (output latch) The data latch (LAT register) is useful for read-modifywrite operations on the value that the I/O pins are driving. CLRF LATA MOVLW MOVWF MOVLW 07h ADCON1 0CFh MOVWF TRISA 9.1 PORTA, TRISA and LATA Registers FIGURE 9-1: RA3:RA0 AND RA5 PINS BLOCK DIAGRAM PORTA is a 6-bit wide, bi-directional port. The corresponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). On a Power-on Reset, these pins are configured as analog inputs and read as '0'. Reading the PORTA register reads the status of the pins, whereas writing to it will write to the port latch. Read-modify-write operations on the LATA register, reads and writes the latched output value for PORTA. The RA4 pin is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/ T0CKI pin is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers. The other PORTA pins are multiplexed with analog inputs and the analog VREF+ and VREF- inputs. The operation of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register1). On a Power-on Reset, these pins are configured as analog inputs and read as '0'. The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. Note: On a Power-on Reset, PORTA pins RA3:RA0 and RA5 default to analog inputs. RD LATA Data Bus D Q VDD WR LATA or WR PORTA CK Q P I/O pin(1) Data Latch D Q N WR TRISA CK Q TRIS Latch VSS Analog Input Mode RD TRISA Q D TTL Input Buffer EN RD PORTA SS Input (RA5 only) To A/D Converter and LVD Modules Note 1: I/O pins have diode protection to VDD and VSS. 2001 Microchip Technology Inc. Advance Information DS39541A-page 103 PIC18C601/801 FIGURE 9-2: RA4/T0CKI PIN BLOCK DIAGRAM RD LATA Data Bus WR LATA or WR PORTA D Q CK Q Data Latch D Q N VSS Schmitt Trigger Input Buffer I/O pin(1) WR TRISA CK Q TRIS Latch RD TRISA Q D EN EN RD PORTA TMR0 Clock Input Note 1: I/O pin has diode protection to VSS only. TABLE 9-1: Name RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI PORTA FUNCTIONS Bit# bit0 bit1 bit2 bit3 bit4 bit5 Buffer TTL TTL TTL TTL TTL Input/output or analog input Input/output or analog input Input/output or analog input or VREFInput/output or analog input or VREF+ Input/output or slave select input for synchronous serial port or analog input or low voltage detect input Function ST/OD Input/output or external clock input for Timer0, output is open drain type RA5/SS/AN4/LVDIN Legend: TTL = TTL input, ST = Schmitt Trigger input, OD = Open Drain TABLE 9-2: Name PORTA LATA TRISA ADCON1 SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 -- -- -- -- Bit 6 -- Bit 5 RA5 Bit 4 RA4 Bit 3 RA3 Bit 2 RA2 Bit 1 RA1 Bit 0 RA0 Value on POR, BOR Value on all other RESETS --0x 0000 --uu uuuu -xxx xxxx -uuu uuuu -111 1111 -111 1111 Latch A Data Output Register PORTA Data Direction Register -- VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 --uu uuuu Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA. DS39541A-page 104 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 9.2 PORTB, TRISB and LATB Registers Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (INTCON2 register). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. Pin RB3 is multiplexed with the CCP input/output. The weak pull-up for RB3 is disabled when the RB3 pin is configured as CCP pin. By disabling the weak pull-up when pin is configured as CCP, allows the remaining weak pull-up devices of PORTB to be used while the CCP is being used. Four of PORTB's pins, RB7:RB4, have an interrupt-onchange feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupton-change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of RB7:RB4 are OR'd together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON register). This interrupt can wake the device from SLEEP. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) Any read or write of PORTB (except with the MOVFF instruction). This will end the mismatch condition. Clear flag bit RBIF. PORTB is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output ( i.e., put the contents of the output latch on the selected pin). Read-modify-write operations on the LATB register read and write the latched output value for PORTB. EXAMPLE 9-2: CLRF PORTB INITIALIZING PORTB ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTB by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RB3:RB0 as inputs RB5:RB4 as outputs RB7:RB6 as inputs CLRF LATB MOVLW 0CFh MOVWF TRISB FIGURE 9-3: RB7:RB4 PINS BLOCK DIAGRAM VDD Weak P Pull-up Data Latch D CK TRIS Latch D Q CK TTL Input Buffer Q I/O pin(1) b) RBPU(2) A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. Data Bus WR LATB or WR PORTB WR TRISB ST Buffer RD TRISB RD LATB Q RD PORTB Set RBIF Latch D EN Q1 From other RB7:RB4 pins Q D RD PORTB EN Q3 RBx/INTx Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2 register). 2001 Microchip Technology Inc. Advance Information DS39541A-page 105 PIC18C601/801 FIGURE 9-4: RB2:RB0 PINS BLOCK DIAGRAM VDD RBPU(2) Data Latch D CK TRIS Latch D Q WR TRIS CK TTL Input Buffer Q I/O pin(1) Weak P Pull-up Data Bus WR Port RD TRIS Q RD Port Schmitt Trigger Buffer RD Port Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2 register). D EN RBx/INTx FIGURE 9-5: RB3 PIN BLOCK DIAGRAM VDD RBPU(2) CCP Enable CCP Output 1 VDD P Enable CCP Output Data Bus WR LATB or WR PORTB 0 Data Latch D CK TRIS Latch Q D WR TRISB CK Q Q N VSS TTL Input Buffer I/O pin(1) Weak P Pull-up RD TRISB RD LATB Q RD PORTB D EN RD PORTB CCP2 Input Schmitt Trigger Buffer Note 1: I/O pin has diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). DS39541A-page 106 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 TABLE 9-3: Name RB0/INT0 RB1/INT1 RB2/INT2 RB3/CCP2 RB4 RB5 RB6 RB7 Legend: Note 1: 2: 3: PORTB FUNCTIONS Bit# bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Buffer TTL/ST(1) TTL/ST(1) TTL/ST(1) TTL/ST(3) TTL TTL TTL/ST(2) TTL/ST(2) Function Input/output pin or external interrupt 0 input. Internal software programmable weak pull-up. Input/output pin or external interrupt 1 input. Internal software programmable weak pull-up. Input/output pin or external interrupt 2 input. Internal software programmable weak pull-up. Input/output pin or Capture2 input or Capture2 output or PWM2 output. Internal software programmable weak pull-up. Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming clock. Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming data. TTL = TTL input, ST = Schmitt Trigger input This pin is a Schmitt Trigger input when configured as the external interrupt. This pin is a Schmitt Trigger input when used in Serial Programming mode. This pin is a Schmitt Trigger input when used in a Capture input. TABLE 9-4: Name PORTB LATB TRISB INTCON INTCON2 INTCON3 SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 RB7 Bit 6 RB6 Bit 5 RB5 Bit 4 RB4 Bit 3 RB3 Bit 2 RB2 Bit 1 RB1 Bit 0 RB0 Value on POR, BOR Value on all other RESETS xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1111 1111 1111 1111 LATB Data Output Register PORTB Data Direction Register GIE/GIEH PEIE/GIEL RBPU INT2IP INTEDG0 INT1IP TMR0IE -- INT0IE INT2IE RBIE INT1IE TMR0IF INT0IF -- -- RBIF RBIP INTEDG1 INTEDG2 INTEDG3 TMR0IP 0000 000x 0000 000u 1111 1111 1111 1111 INT2IF INT1IF 1100 0000 1100 0000 Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTD. 2001 Microchip Technology Inc. Advance Information DS39541A-page 107 PIC18C601/801 9.3 PORTC, TRISC and LATC Registers The pin override value is not loaded into the TRIS register. This allows read-modify-write of the TRIS register, without concern due to peripheral overrides. PORTC is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). Read-modify-write operations on the LATC register, read and write the latched output value for PORTC. PORTC is multiplexed with several peripheral functions (Table 9-5). PORTC pins have Schmitt Trigger input buffers. When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. EXAMPLE 9-3: CLRF PORTC INITIALIZING PORTC ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTC by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RC3:RC0 as inputs RC5:RC4 as outputs RC7:RC6 as inputs CLRF LATC MOVLW 0CFh MOVWF TRISC FIGURE 9-6: PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE) Peripheral Out Select Peripheral Data Out 0 1 VDD P RD LATC Data Bus WR LATC or WR PORTC D CK Q Q TRIS OVERRIDE N TRIS Override VSS Pin RC0 RC1 RC2 Peripheral Enable RD TRISC Q D EN RD PORTC Peripheral Data In RC7 Yes Schmitt Trigger RC3 RC4 RC5 RC6 Override Peripheral Yes Yes No Yes Yes Yes Yes Timer1 OSC for Timer1/Timer3 Timer1 OSC for Timer1/Timer3 -- SPI/I2C Master Clock I2C Data Out SPI Data Out USART Async Xmit, Sync Clock USART Sync Data Out I/O pin(1) Data Latch D Q Q WR TRISC CK TRIS Latch Note 1: I/O pins have diode protection to VDD and VSS. DS39541A-page 108 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 TABLE 9-5: Name RC0/T1OSO/T13CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT PORTC FUNCTIONS Bit# bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Buffer Type ST ST ST ST ST ST ST ST Function Input/output port pin or Timer1 oscillator output or Timer1/Timer3 clock input. Input/output port pin, Timer1 oscillator input. Input/output port pin or Capture1 input/Compare1 output/ PWM1 output. Input/output port pin or synchronous serial clock for SPI/I2C. Input/output port pin or SPI Data in (SPI mode) or Data I/O (I2C mode). Input/output port pin or Synchronous Serial Port Data output. Input/output port pin, Addressable USART Asynchronous Transmit, or Addressable USART Synchronous Clock. Input/output port pin, Addressable USART Asynchronous Receive, or Addressable USART Synchronous Data. Legend: ST = Schmitt Trigger input TABLE 9-6: Name PORTC LATC TRISC SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 7 RC7 Bit 6 RC6 Bit 5 RC5 Bit 4 RC4 Bit 3 RC3 Bit 2 RC2 Bit 1 RC1 Bit 0 RC0 Value on POR, BOR xxxx xxxx xxxx xxxx 1111 1111 Value on all other RESETS uuuu uuuu uuuu uuuu 1111 1111 LATC Data Output Register PORTC Data Direction Register Legend: x = unknown, u = unchanged 2001 Microchip Technology Inc. Advance Information DS39541A-page 109 PIC18C601/801 9.4 PORTD, TRISD and LATD Registers FIGURE 9-7: PORTD BLOCK DIAGRAM IN I/O MODE PORTD is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e., put the contents of the output latch on the selected pin). Read-modify-write operations on the LATD register reads and writes the latched output value for PORTD. PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. PORTD is multiplexed with the system bus and is available only when the system bus is disabled, by setting EBIDS bit in register MEMCON. When operating as the system bus, PORTD is the low order byte of the address/data bus (AD7:AD0), or as the low order address byte (A15:A8) if the address and data buses are de-multiplexed. Note: On a Power-on Reset, PORTD defaults to the system bus. RD LATD Data Bus WR LATD or WR PORTD D Q I/O pin CK Data Latch D WR TRISD Q Schmitt Trigger Input Buffer CK TRIS Latch RD TRISD Q D EN EN RD PORTD Note: I/O pins have diode protection to VDD and VSS. EXAMPLE 9-4: CLRF PORTD INITIALIZING PORTD ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTD by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RD3:RD0 as inputs RD5:RD4 as outputs RD7:RD6 as inputs CLRF LATD MOVLW 0CFh MOVWF TRISD DS39541A-page 110 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 FIGURE 9-8: PORTD BLOCK DIAGRAM IN SYSTEM BUS MODE Q D EN EN RD PORTD RD LATD Data Bus WR LATD or PORTD D CK Data Latch D WR TRISD CK TRIS Latch Q Q Port Data 0 1 I/O pin(1) TTL Input Buffer Bus Enable System Bus Data/TRIS Out Control Drive Bus RD TRISD Instruction Register Instruction Read Note 1: I/O pins have protection diodes to VDD and VSS. 2001 Microchip Technology Inc. Advance Information DS39541A-page 111 PIC18C601/801 TABLE 9-7: Name RD0/AD0/A0(2) RD1/AD1/A1(2) RD2/AD2/A2(2) RD3/AD3/A3 RD5/AD5/A5 (2) PORTD FUNCTIONS Bit# bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Buffer Type ST/TTL(1) ST/TTL(1) ST/TTL(1) ST/TTL ST/TTL (1) Function Input/output port pin or system bus bit 0 Input/output port pin or system bus bit 1 Input/output port pin or system bus bit 2 Input/output port pin or system bus bit 3 Input/output port pin or system bus bit 4 Input/output port pin or system bus bit 5 Input/output port pin or system bus bit 6 Input/output port pin or system bus bit 7 RD4/AD4/A4(3) (2) ST/TTL(1) (1) RD6/AD6/A6(2) RD7/AD7/A7(2) ST/TTL(1) ST/TTL(1) Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in System Bus mode. 2: RDx is used as a multiplexed address/data bus for PIC18C601 and PIC18C801 in 16-bit mode, and as an address only for PIC18C801 in 8-bit mode. TABLE 9-8: Name PORTD LATD TRISD MEMCON SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Bit 7 RD7 Bit 6 RD6 Bit 5 RD5 Bit 4 RD4 Bit 3 RD3 Bit 2 RD2 Bit 1 RD1 Bit 0 RD0 Value on POR, BOR xxxx xxxx xxxx xxxx 1111 1111 Value on all other RESETS uuuu uuuu uuuu uuuu 1111 1111 0000 --00 LATD Data Output Register PORTD Data Direction Register EBDIS PGRM WAIT1 WAIT0 -- -- WM1 WM0 0000 --00 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTD. DS39541A-page 112 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 9.5 PORTE, TRISE and LATE Registers byte of the address/data bus (AD15:AD8), or as the high order address byte (A15:A8), if address and data buses are de-multiplexed. Note: On Power-on Reset, PORTE defaults to the system bus. PORTE is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., put the contents of the output latch on the selected pin). Read-modify-write operations on the LATE register reads and writes the latched output value for PORTE. PORTE is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. PORTE is multiplexed with several peripheral functions (Table 9-9). PORTE is multiplexed with the system bus and is available only when the system bus is disabled, by setting EBDIS bit in register MEMCON. When operating as the system bus, PORTE is configured as the high order EXAMPLE 9-5: CLRF PORTE INITIALIZING PORTE ; ; ; ; ; ; ; ; ; ; ; Initialize PORTE by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RE1:RE0 as inputs RE7:RE2 as outputs CLRF LATE MOVLW 03h MOVWF TRISE FIGURE 9-9: PORTE BLOCK DIAGRAM IN I/O MODE Peripheral Out Select Peripheral Data Out 0 1 RD LATE Data Bus WR LATE or WR PORTE D CK Q Q N TRIS Override VSS Pin RE0 RE1 Peripheral Enable RD TRISE Q D EN RD PORTE Peripheral Data In Note 1: I/O pins have diode protection to VDD and VSS. Schmitt Trigger RE2 RE3 RE4 RE5 RE6 RE7 TRIS OVERRIDE Override Yes Yes Yes Yes Yes Yes Yes Yes Peripheral External Bus External Bus External Bus External Bus External Bus External Bus External Bus External Bus VDD P I/O pin(1) Data Latch D Q Q WR TRISE CK TRIS Latch 2001 Microchip Technology Inc. Advance Information DS39541A-page 113 PIC18C601/801 FIGURE 9-10: PORTE BLOCK DIAGRAM IN SYSTEM BUS MODE Q D EN EN RD PORTE RD LATD Data Bus WR LATE or PORTE D Q Port Data CK 0 1 I/O pin(1) Data Latch TRIS Latch D Q WR TRISE CK TTL Input Buffer External Enable System Bus Control Data/Address Out Drive System RD TRISE To Instruction Register Instruction Read Note 1: I/O pins have diode protection to VDD and VSS. DS39541A-page 114 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 TABLE 9-9: Name PORTE FUNCTIONS Bit# Buffer Type Function RE0/AD8/A8(2) bit0 ST/TTL(1) Input/output port pin or Address/Data bit 8 (2) RE1/AD9/A9 bit1 ST/TTL(1) Input/output port pin or Address/Data bit 9 RE2/AD10/A10(2) bit2 ST/TTL(1) Input/output port pin or Address/Data bit 10 RE3/AD11/A11(2) bit3 ST/TTL(1) Input/output port pin or Address/Data bit 11 (2) (1) RE4/AD12/A12 bit4 ST/TTL Input/output port pin or Address/Data bit 12 RE5/AD13/A13(2) bit5 ST/TTL(1) Input/output port pin or Address/Data bit 13 RE6/AD14/A14(2) bit6 ST/TTL(1) Input/output port pin or Address/Data bit 14 RE7/AD15/A15(2) bit7 ST/TTL(1) Input/output port pin or Address/Data bit 15 Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in System Bus mode. 2: REx is used as a multiplexed address/data bus for PIC18C601 and PIC18C801 in 16-bit mode, and as an address only for PIC18C801 in 8-bit mode. TABLE 9-10: Name TRISE PORTE LATE MEMCON SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR 1111 1111 xxxx xxxx xxxx xxxx Value on all other RESETS 1111 1111 uuuu uuuu uuuu uuuu 0000 --00 PORTE Data Direction Control Register Read PORTE pin/Write PORTE Data Latch Read PORTE Data Latch/Write PORTE Data Latch EBDIS PGRM WAIT1 WAIT0 -- -- WM1 WM0 0000 --00 Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTE. 2001 Microchip Technology Inc. Advance Information DS39541A-page 115 PIC18C601/801 9.6 PORTF, LATF, and TRISF Registers EXAMPLE 9-7: PROGRAMMING CHIP SELECT SIGNALS PORTF is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISF. Setting a TRISF bit (= 1) will make the corresponding PORTF pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISF bit (= 0) will make the corresponding PORTF pin an output (i.e., put the contents of the output latch on the selected pin). Read-modify-write operations on the LATF register reads and writes the latched output value for PORTF. PORTF pins, RF2:RF0, are multiplexed with analog inputs. The operation of these pins are selected by ADCON0 and ADCON1 registers. PORTF pins, RF3 and RF5, are multiplexed with two of the integrated chip select signals CSIO and CS1. For PIC18C801, pin RF4 is multiplexed with chip select signal CS2, while for PIC18C601, it is multiplexed with system bus signal A16. For PIC18C801 devices, both CSEL2 and CSELIO registers must set to all zero, to enable these pins as I/O pins, while for PIC18C601 devices, only CSELIO register needs to be set to zero. For PIC18C601 devices, pin RF4 can only be configured as I/O when the EBDIS bit is set and execution is taking place in internal Boot RAM. PORTF pins, RF7:RF6, are multiplexed with the system bus control signal UB and LB, respectively, when a device with 16-bit bus execution is used. These pins can be configured as I/O pins by setting WM bits in the MEMCON register to any value other than '01'. Note 1: On Power-on Reset, PORTF RF2:RF0 default to A/D inputs. pins * * ; Program chip select to activate CS1 ; for all address less than 03FFFFh, ; while activate CS2 for rests of the ; addresses ; CSEL2 register is secured register. ; Before it can be modified it, ; combination lock must be opened MOVLW 20h ; Preload WREG with ; correct CSEL2 valu BCF INTCON, GIE ; Disable interrupts CALL UNLOCK ; Now unlock it ; Lock is open. Modify CSEL2... MOVWF CSEL2 ; Lock is closed BSF INTCON, GIE ; Re-enable interrupts ; Chip select is programmed. * * UNLOCK BSF PSPCON, CMLK1 BSF PSPCON, CMLK0 RETURN * * FIGURE 9-11: RF2:RF0 PINS BLOCK DIAGRAM RD LATF Data Bus D Q VDD WR LATF or WR PORTF CK Q P I/O pin 2: On Power-on Reset, PORTF pins RF7:RF3 for PIC18C801 and pins RF7:RF5, RF3 for PIC18C601, default to system bus signals. Data Latch D Q N EXAMPLE 9-6: CLRF PORTF INITIALIZING PORTF ; ; ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTF by clearing output data latches Alternate method to clear output data latches Set PORTF as digital I/O Value used to initialize data direction Set RF3:RF0 as inputs RF5:RF4 as outputs RF7:RF6 as inputs WR TRISF CK Q VSS Analog Input Mode TRIS Latch CLRF LATF RD TRISF Q D MOVLW MOVWF MOVLW 0Fh ADCON1 0CFh ST Input Buffer EN RD PORTF To A/D Converter Note: I/O pins have diode protection to VDD and VSS. MOVWF TRISF DS39541A-page 116 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 FIGURE 9-12: RF5:RF3 PINS BLOCK DIAGRAM Q D EN EN RD PORTF RD LATF Data Bus WR LATF or PORTF D Q Port Data CK 0 1 I/O pin(1) Data Latch TRIS Latch D Q WR TRISF CK CS Out System Bus Control External Enable Drive System RD TRISF Note 1: I/O pins have diode protection to VDD and VSS. FIGURE 9-13: RF7:RF6 PINS BLOCK DIAGRAM Q D EN EN RD PORTF RD LATF Data Bus WR LATF or PORTF D Q Port Data CK 0 1 I/O pin(1) Data Latch TRIS Latch D Q WR TRISF CK UB/LB Out System Bus Control WM = '01' Drive System RD TRISF Note 1: I/O pins have diode protection to VDD and VSS. 2001 Microchip Technology Inc. Advance Information DS39541A-page 117 PIC18C601/801 TABLE 9-11: Name PORTF FUNCTIONS Bit# Buffer Type Function Input/output port pin or analog input Input/output port pin or analog input Input/output port pin or analog input Input/output port pin or I/O chip select Input/output port pin or chip select 2 or address bit 16 Input/output port pin or chip select 1 Input/output port pin or low byte select signal for external memory Input/output port pin or high byte select signal for external memory RF0/AN5 bit0 ST RF1/AN6 bit1 ST RF2/AN7 bit2 ST RF3/CSIO bit3 ST (1) RF4/A16/CS2 bit4 ST RF5/CS1 bit5 ST RF6/LB bit6 ST RF7/UB bit7 ST Legend: ST = Schmitt Trigger input Note 1: CS2 is available only on PIC18C801. TABLE 9-12: Name TRISF PORTF LATF ADCON1 MEMCON SUMMARY OF REGISTERS ASSOCIATED WITH PORTF Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR 1111 1111 xxxx xxxx 0000 0000 --00 0000 0000 --00 Value on all other RESETS 1111 1111 uuuu uuuu uuuu uuuu --00 0000 0000 --00 PORTF Data Direction Control Register Read PORTF pin/Write PORTF Data Latch Read PORTF Data Latch/Write PORTF Data Latch -- EBDIS -- PGRM VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 WAIT1 WAIT0 -- -- WM1 WM0 Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTF. DS39541A-page 118 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 9.7 PORTG, LATG, and TRISG Registers FIGURE 9-14: PORTG BLOCK DIAGRAM IN I/O MODE PORTG is a 5-bit wide, bi-directional port. The corresponding data direction register is TRISG. Setting a TRISG bit (= 1) will make the corresponding PORTG pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISG bit (= 0) will make the corresponding PORTG pin an output (i.e., put the contents of the output latch on the selected pin). Read-modify-write operations on the LATG register read and write the latched output value for PORTG. PORTG is multiplexed with system bus control signals ALE, OE, WRH, WRL and BA0. The WRH signal is the only signal that is disabled and configured as a port pin (RG3) during external program execution in 8-bit mode. All other pins are by default, system bus control signals. PORTG can be configured as an I/O port by setting EBDIS bit in the MEMCON register and when execution is taking place in internal program RAM. Note: On Power-on Reset, PORTG defaults to system bus signals. Data Bus WR LATG or PORTG RD LATG D Q I/O pin(1) CK Data Latch D Q WR TRISG CK TRIS Latch Schmitt Trigger Input Buffer RD TRISG Q D EN EN RD PORTG EXAMPLE 9-8: CLRF PORTG INITIALIZING PORTG ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTG by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RG1:RG0 as outputs RG2 as input RG4:RG3 as outputs Note 1: I/O pins have diode protection to VDD and VSS. CLRF LATG MOVLW 04h MOVWF TRISG 2001 Microchip Technology Inc. Advance Information DS39541A-page 119 PIC18C601/801 FIGURE 9-15: PORTG BLOCK DIAGRAM IN SYSTEM BUS MODE Q D EN EN RD PORTG RD LATG Data Bus WR LATG or PORTG D Q Port 0 Data 1 I/O pin(1) CK Data Latch D Q WR TRISG CK TRIS Latch Control Out System Bus Control External Enable Drive System RD TRISG Note 1: I/O pins have diode protection to VDD and VSS. TABLE 9-13: Name PORTG FUNCTIONS Bit# Buffer Type Function Input/output port pin or Address Latch Enable signal for external memory Input/output port pin or Output Enable signal for external memory Input/output port pin or Write Low byte signal for external memory Input/output port pin or Write High byte signal for external memory Input/output port pin or Byte Address 0 signal for external memory RG0/ALE bit0 ST RG1/OE bit1 ST RG2/WRL bit2 ST RG3/WRH bit3 ST RG4/BA0 bit4 ST Legend: ST = Schmitt Trigger input TABLE 9-14: Name TRISG PORTG LATG MEMCON SUMMARY OF REGISTERS ASSOCIATED WITH PORTG Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR ---1 1111 ---x xxxx ---x xxxx Value on all other RESETS ---1 1111 ---u uuuu ---u uuuu 0000 --00 PORTG Data Direction Control Register Read PORTG pin/Write PORTG Data Latch Read PORTG Data Latch/Write PORTG Data Latch EBDIS PGRM WAIT1 WAIT0 -- -- WM1 WM0 0000 --00 Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTG. DS39541A-page 120 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 9.8 Note: PORTH, LATH, and TRISH Registers PORTH is available only on PIC18C801 devices. FIGURE 9-16: RH3:RH0 PINS BLOCK DIAGRAM IN I/O MODE PORTH is an 8-bit wide, bi-directional I/O port. The corresponding data direction register is TRISH. Setting a TRISH bit (= 1) will make the corresponding PORTH pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISH bit (= 0) will make the corresponding PORTH pin an output (i.e., put the contents of the output latch on the selected pin). Read-modify-write operations on the LATH register read and write the latched output value for PORTH. Pins RH7:RH4 are multiplexed with analog inputs AN18:AN11, while pins RH3:RH0 are multiplexed with system address bus A19:A16. By default, pins RH7:RH4 will setup as A/D inputs and pins RH3:RH0 will setup as system address bus. Register ADCON1 configures RH7:RH4 as I/O or A/D inputs. Register MEMCON configures RH3:RH0 as I/O or system bus pins. Note 1: On Power-on Reset, PORTH pins RH7:RH4 default to A/D inputs and read as '0'. 2: On Power-on Reset, PORTH pins RH3:RH0 default to system bus signals. Data Bus WR LATH or PORTH RD LATH D Q I/O pin(1) CK Data Latch D Q WR TRISH CK TRIS Latch Schmitt Trigger Input Buffer RD TRISH Q D EN EN RD PORTH Note 1: I/O pins have diode protection to VDD and VSS. FIGURE 9-17: EXAMPLE 9-9: CLRF PORTH INITIALIZING PORTH ; ; ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTH by clearing output data latches Alternate method to clear output data latches RH7:RH4 PINS BLOCK DIAGRAM CLRF LATH Data Bus WR LATH or PORTH RD LATH D Q I/O pin(1) CK MOVLW MOVWF MOVLW 0Fh ADCON1 0CFh Data Latch D Q MOVWF TRISH Value used to initialize data direction Set RH3:RH0 as inputs RH5:RH4 as outputs RH7:RH6 as inputs WR TRISH CK TRIS Latch Schmitt Trigger Input Buffer RD TRISH Q D EN EN RD PORTH To A/D Converter Note 1: I/O pins have diode protection to VDD and VSS. 2001 Microchip Technology Inc. Advance Information DS39541A-page 121 PIC18C601/801 FIGURE 9-18: RH3:RH0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE Q D EN EN RD PORTH RD LATD Data Bus WR LATH or PORTH D Q Port 0 Data 1 I/O pin(1) CK Data Latch D Q WR TRISH CK TRIS Latch TTL Input Buffer External Enable. System Bus Control Address Out Drive System RD TRISH To Instruction Register Instruction Read Note 1: I/O pins have diode protection to VDD and VSS. DS39541A-page 122 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 TABLE 9-15: Name RH0/A16(1) PORTH FUNCTIONS Bit# Buffer Type Function bit0 ST Input/output port pin or Address bit 16 for external memory interface RH1/A17(1) bit1 ST Input/output port pin or Address bit 17 for external memory interface (1) RH2/A18 bit2 ST Input/output port pin or Address bit 18 for external memory interface RH3/A19(1) bit3 ST Input/output port pin or Address bit 19 for external memory interface RH4/AN8(1) bit4 ST Input/output port pin or analog input channel 8 RH5/AN9(1) bit5 ST Input/output port pin or analog input channel 9 (1) RH6/AN10 bit6 ST Input/output port pin or analog input channel 10 RH7/AN11(1) bit7 ST Input/output port pin or analog input channel 11 Legend: ST = Schmitt Trigger input Note 1: PORTH is available only on PIC18C801 devices. TABLE 9-16: Name TRISH PORTH LATH ADCON1 MEMCON SUMMARY OF REGISTERS ASSOCIATED WITH PORTH Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR 1111 1111 xxxx xxxx xxxx xxxx --00 0000 0000 --00 Bit 7 Value on all other RESETS 1111 1111 uuuu uuuu uuuu uuuu --00 0000 0000 --00 PORTH Data Direction Control Register Read PORTH pin/Write PORTH Data Latch Read PORTH Data Latch/Write PORTH Data Latch -- EBDIS -- PGRM VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 WAIT1 WAIT0 -- -- WM1 WM0 Legend: x = unknown, u = unchanged, - = unimplemented. Shaded cells are not used by PORTH. 2001 Microchip Technology Inc. Advance Information DS39541A-page 123 PIC18C601/801 9.9 Note: PORTJ, LATJ, and TRISJ Registers PORTJ is available only on PIC18C801 devices. FIGURE 9-19: PORTJ BLOCK DIAGRAM IN I/O MODE PORTJ is an 8-bit wide, bi-directional I/O port. The corresponding data direction register is TRISJ. Setting a TRISJ bit (= 1) will make the corresponding PORTJ pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISJ bit (= 0) will make the corresponding PORTJ pin an output (i.e., put the contents of the output latch on the selected pin). Read-modify-write operations on the LATJ register read and write the latched output value for PORTJ. PORTJ is multiplexed with de-multiplexed system data bus D7:D0, when device is configured in 8-bit execution mode. Register MEMCON configures PORTJ as I/O or system bus pins. Note: On Power-on Reset, PORTJ defaults to system bus signals. Data Bus WR LATJ or PORTJ RD LATJ D Q I/O pin(1) CK Data Latch D Q WR TRISJ CK TRIS Latch Schmitt Trigger Input Buffer RD TRISJ Q D EN EN RD PORTJ EXAMPLE 9-10: CLRF PORTJ INITIALIZING PORTJ ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTJ by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RJ3:RJ0 as inputs RJ5:RJ4 as outputs RJ7:RJ6 as inputs Note 1: I/O pins have diode protection to VDD and VSS. CLRF LATJ MOVLW 0CFh MOVWF TRISJ DS39541A-page 124 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 FIGURE 9-20: PORTJ BLOCK DIAGRAM IN SYSTEM DATA BUS MODE Q D EN EN RD PORTJ RD LATD Data Bus WR LATJ or PORTJ D Q Port I/O pin(1) 0 Data 1 CK Data Latch TRIS Latch D Q WR TRISJ CK S R TTL Input Buffer External Enable System Bus Control Data Out Drive System RD TRISJ To Instruction Register Instruction Read Note 1: I/O pins have diode protection to VDD and VSS. 2001 Microchip Technology Inc. Advance Information DS39541A-page 125 PIC18C601/801 TABLE 9-17: Name RJ0/D0(1) PORTJ FUNCTIONS Bit# Buffer Type Function or Data bit 0 for external memory interface or Data bit 1 for external memory interface or Data bit 2 for external memory interface or Data bit 3 for external memory interface or Data bit 4 for external memory interface or Data bit 5 for external memory interface or Data bit 6 for external memory interface or Data bit 7 for external memory interface bit0 ST/TTL Input/output port pin RJ1/D1(1) bit1 ST/TTL Input/output port pin RJ2/D2(1) bit2 ST/TTL Input/output port pin RJ3/D3(1) bit3 ST/TTL Input/output port pin RJ4/D4(1) bit4 ST/TTL Input/output port pin RJ5/D5(1) bit5 ST/TTL Input/output port pin (1) RJ6/D6 bit6 ST/TTL Input/output port pin RJ7/D7(1) bit7 ST/TTL Input/output port pin Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: PORTJ is available only on PIC18C801 devices. TABLE 9-18: Name TRISJ PORTJ LATJ MEMCON SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR 1111 1111 xxxx xxxx xxxx xxxx Value on all other RESETS 1111 1111 uuuu uuuu uuuu uuuu 0000 --00 PORTJ Data Direction Control Register Read PORTJ pin/Write PORTJ Data Latch Read PORTJ Data Latch/Write PORTJ Data Latch EBDIS PGRM WAIT1 WAIT0 -- -- WM1 WM0 0000 --00 Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTJ. DS39541A-page 126 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 10.0 TIMER0 MODULE Register 10-1 shows the Timer0 Control register (T0CON). Figure 10-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure 10-2 shows a simplified block diagram of the Timer0 module in 16-bit mode. The T0CON register is a readable and writable register that controls all the aspects of Timer0, including the prescale selection. Note: Timer0 is enabled on POR. The Timer0 module has the following features: * Software selectable as an 8-bit or 16-bit timer/ counter * Readable and writable * Dedicated 8-bit software programmable prescaler * Clock source selectable to be external or internal * Interrupt on overflow from FFh to 00h in 8-bit mode and FFFFh to 0000h in 16-bit mode * Edge select for external clock REGISTER 10-1: T0CON REGISTER R/W-1 TMR0ON bit 7 R/W-1 T08BIT R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 T0PS2 R/W-1 T0PS1 R/W-1 T0PS0 bit 0 bit 7 TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 T08BIT: Timer0 8-bit/16-bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. T0PS2:T0PS0: Timer0 Prescaler Select bits 111 = 1:256 prescale value 110 = 1:128 prescale value 101 = 1:64 prescale value 100 = 1:32 prescale value 011 = 1:16 prescale value 010 = 1:8 prescale value 001 = 1:4 prescale value 000 = 1:2 prescale value Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 6 bit 5 bit 4 bit 3 bit 2-0 2001 Microchip Technology Inc. Advance Information DS39541A-page 127 PIC18C601/801 FIGURE 10-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE Data Bus FOSC/4 0 8 0 1 RA4/T0CKI pin(2) T0SE Programmable Prescaler 1 Sync with Internal Clocks (2 TCY delay) TMR0L 3 T0PS2, T0PS1, T0PS0 T0CS(1) PSA Set Interrupt Flag bit TMR0IF on Overflow Note 1: Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. 2: I/O pins have diode protection to VDD and VSS. FIGURE 10-2: TIMER0 BLOCK DIAGRAM IN 16-BIT MODE FOSC/4 0 0 1 Sync with Internal Clocks (2 TCY delay) TMR0L TMR0 High Byte 8 Set Interrupt Flag bit TMR0IF on Overflow RA4/T0CKI pin(2) T0SE Programmable Prescaler 3 T0PS2, T0PS1, T0PS0 T0CS(1) 1 Read TMR0L Write TMR0L PSA 8 8 TMR0H 8 Data Bus<7:0> Note 1: Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. 2: I/O pins have diode protection to VDD and VSS. DS39541A-page 128 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 10.1 Timer0 Operation 10.2.1 Timer0 can operate as a timer or as a counter. Timer mode is selected by clearing the T0CS bit. In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0L register is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0L register. Counter mode is selected by setting the T0CS bit. In Counter mode, Timer0 will increment either on every rising, or falling edge, of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit (T0SE). Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed below. When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure the external clock can be synchronized with the internal phase clock (TOSC). Also, there is a delay in the actual incrementing of Timer0 after synchronization. SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control (i.e., it can be changed "on-the-fly" during program execution). 10.3 Timer0 Interrupt The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h in 8-bit mode, or FFFFh to 0000h in 16-bit mode. This overflow sets the TMR0IF bit. The interrupt can be masked by clearing the TMR0IE bit. The TMR0IF bit must be cleared in software by the Timer0 module Interrupt Service Routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from SLEEP, since the timer is shut-off during SLEEP. 10.4 16-Bit Mode Timer Reads and Writes 10.2 Prescaler Timer0 can be set in 16-bit mode by clearing T0CON T08BIT. Registers TMR0H and TMR0L are used to access 16-bit timer value. TMR0H is not the high byte of the timer/counter in 16-bit mode, but is actually a buffered version of the high byte of Timer0 (refer to Figure 10-1). The high byte of the Timer0 counter/timer is not directly readable nor writable. TMR0H is updated with the contents of the high byte of Timer0 during a read of TMR0L. This provides the ability to read all 16-bits of Timer0 without having to verify that the read of the high and low byte were valid, due to a rollover between successive reads of the high and low byte. A write to the high byte of Timer0 must also take place through the TMR0H buffer register. Timer0 high byte is updated with the contents of the buffered value of TMR0H, when a write occurs to TMR0L. This allows all 16-bits of Timer0 to be updated at once. An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not readable or writable. The PSA and T0PS2:T0PS0 bits determine the prescaler assignment and prescale ratio. Clearing bit PSA will assign the prescaler to the Timer0 module. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g. CLRF TMR0, MOVWF TMR0, BSF TMR0, x.... etc.) will clear the prescaler count. Note: Writing to TMR0 when the prescaler is assigned to Timer0, will clear the prescaler count but will not change the prescaler assignment. TABLE 10-1: Name TMR0L TMR0H INTCON T0CON TRISA REGISTERS ASSOCIATED WITH TIMER0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR xxxx xxxx 0000 0000 Value on all other RESETS uuuu uuuu 0000 0000 0000 000u 1111 1111 --11 1111 Timer0 Module's Low Byte Register Timer0 Module's High Byte Register GIE/GIEH TMR0ON -- PEIE/GIEL TMR0IE INT0IE T08BIT T0CS T0SE PORTA Data Direction Register RBIE PSA TMR0IF INT0IF T0PS2 RBIF 0000 000x T0PS1 T0PS0 1111 1111 --11 1111 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0. 2001 Microchip Technology Inc. Advance Information DS39541A-page 129 PIC18C601/801 11.0 TIMER1 MODULE The Timer1 module timer/counter has the following features: * 16-bit timer/counter (Two 8-bit registers: TMR1H and TMR1L) * Readable and writable (both registers) * Internal or external clock select * Interrupt on overflow from FFFFh to 0000h * RESET from CCP module special event trigger Register 11-1 shows the Timer1 Control register. This register controls the operating mode of the Timer1 module as well as contains the Timer1 oscillator enable bit (T1OSCEN). Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON register). Figure 11-1 is a simplified block diagram of the Timer1 module. Note: Timer1 is disabled on POR. REGISTER 11-1: T1CON REGISTER R/W-0 RD16 bit 7 U-0 -- R/W-0 T1CKPS1 R/W-0 T1CKPS0 R/W-0 T1OSCEN R/W-0 T1SYNC R/W-0 TMR1CS R/W-0 TMR1ON bit 0 bit 7 RD16: 16-bit Read/Write Mode Enable bit 1 = Enables register Read/Write of TImer1 in one 16-bit operation 0 = Enables register Read/Write of Timer1 in two 8-bit operations Unimplemented: Read as '0' T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value T1OSCEN: Timer1 Oscillator Enable bit 1 = Timer1 Oscillator is enabled 0 = Timer1 Oscillator is shut-off The oscillator inverter and feedback resistor are turned off to eliminate power drain. T1SYNC: Timer1 External Clock Input Synchronization Select bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge) 0 = Internal clock (FOSC/4) TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 6 bit 5-4 bit 3 bit 2 bit 1 bit 0 DS39541A-page 130 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 11.1 Timer1 Operation Timer1 can operate in one of these modes: * As a timer * As a synchronous counter * As an asynchronous counter The operating mode is determined by the clock select bit, TMR1CS (T1CON register). Note: When Timer1 is configured in an Asynchronous mode, care must be taken to make sure that there is no incoming pulse while Timer1 is being turned off. If there is an incoming pulse while Timer1 is being turned off, Timer1 value may become unpredictable. If an application requires that Timer1 be turned off and if it is possible that Timer1 may receive an incoming pulse while being turned off, synchronize the external clock first, by clearing the T1SYNC bit of register T1CON. Please note that this may cause Timer1 to miss up to one count. When TMR1CS is clear, Timer1 increments every instruction cycle. When TMR1CS is set, Timer1 increments on every rising edge of the external clock input or the Timer1 oscillator, if enabled. When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is ignored. Timer1 also has an internal "RESET input". This RESET can be generated by the CCP module (Table 14.0). FIGURE 11-1: TMR1IF Overflow Interrupt Flag Bit TIMER1 BLOCK DIAGRAM CCP Special Event Trigger TMR1 TMR1H CLR TMR1L TMR1ON On/Off T1OSC 0 1 T1SYNC Prescaler 1, 2, 4, 8 0 2 T1CKPS1:T1CKPS0 TMR1CS SLEEP Input Synchronize det Synchronized Clock Input T13CKI/T1OSO T1OSI T1OSCEN Enable Oscillator(1) 1 FOSC/4 Internal Clock Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain. 2001 Microchip Technology Inc. Advance Information DS39541A-page 131 PIC18C601/801 FIGURE 11-2: Data Bus<7:0> 8 TMR1H 8 Write TMR1L Read TMR1L TMR1IF Overflow Interrupt Flag bit 8 Timer 1 High Byte TMR1 TMR1L 1 TMR1ON On/Off T1OSC T13CKI/T1OSO T1OSCEN Enable Oscillator(1) FOSC/4 Internal Clock 1 Prescaler 1, 2, 4, 8 0 2 TMR1CS T1CKPS1:T1CKPS0 Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain. SLEEP Input Synchronize det T1SYNC Special Event Trigger 0 Synchronized Clock Input 8 TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE T1OSI DS39541A-page 132 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 11.2 Timer1 Oscillator 11.4 A crystal oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit T1OSCEN (T1CON register). The oscillator is a low power oscillator rated up to 200 kHz. It will continue to run during SLEEP. It is primarily intended for a 32 kHz crystal. Table 11-1 shows the capacitor selection for the Timer1 oscillator. The user must provide a software time delay to ensure proper start-up of the Timer1 oscillator. Resetting Timer1 using a CCP Trigger Output If the CCP module is configured in Compare mode to generate a "special event trigger" (CCP1M3:CCP1M0 = 1011), this signal will reset Timer1 and start an A/D conversion (if the A/D module is enabled). Note: The special event triggers from the CCP1 module will not set interrupt flag bit TMR1IF (PIR registers). TABLE 11-1: CAPACITOR SELECTION FOR THE ALTERNATE OSCILLATOR Freq 32 kHz C1 TBD(1) C2 TBD(1) Timer1 must be configured for either Timer, or Synchronized Counter mode, to take advantage of this feature. If Timer1 is running in Asynchronous Counter mode, this RESET operation may not work. In the event that a write to Timer1 coincides with a special event trigger from CCP1, the write will take precedence. In this mode of operation, the CCPR1H:CCPR1L registers pair, effectively becomes the period register for Timer1. Osc Type LP Crystal to be Tested: 32.768 kHz Epson C-001R32.768K-A 20 PPM Note 1: Microchip suggests 33 pF as a starting point in validating the oscillator circuit. 2: Higher capacitance increases the stability of the oscillator, but also increases the start-up time. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: Capacitor values are for design guidance only. 11.5 Timer1 16-Bit Read/Write Mode 11.3 Timer1 Interrupt Timer1 can be configured for 16-bit reads and writes (see Figure 11-2). When the RD16 control bit (T1CON register) is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high byte of Timer1 into the Timer1 high byte buffer. This provides the user with the ability to accurately read all 16 bits of Timer1, without having to determine whether a read of the high byte followed by a read of the low byte is valid, due to a rollover between reads. A write to the high byte of Timer1 must also take place through the TMR1H buffer register. Timer1 high byte is updated with the contents of TMR1H when a write occurs to TMR1L. This allows a user to write all 16-bits to both the high and low bytes of Timer1 at once. The high byte of Timer1 is not directly readable or writable in this mode. All reads and writes must take place through the Timer1 high byte buffer register. Writes to TMR1H do not clear the Timer1 prescaler. The prescaler is only cleared on writes to TMR1L. The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit TMR1IF (PIR registers). This interrupt can be enabled/disabled by setting/ clearing TMR1 interrupt enable bit TMR1IE (PIE registers). 2001 Microchip Technology Inc. Advance Information DS39541A-page 133 PIC18C601/801 TABLE 11-2: Name INTCON PIR1 PIE1 IPR1 TMR1L TMR1H T1CON Legend: Bit 7 GIE/ GIEH -- -- -- REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Bit 6 PEIE/ GIEL ADIF ADIE ADIP Bit 5 TMR0IE RCIF RCIE RCIP Bit 4 INT0IE TXIF TXIE TXIP Bit 3 RBIE SSPIF SSPIE SSPIP Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP Value on POR, BOR Value on all other RESETS 0000 000x 0000 000u -000 0000 -000 0000 -000 0000 -000 0000 -000 0000 -000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu Holding register for the Least Significant Byte of the 16-bit TMR1 register Holding register for the Most Significant Byte of the 16-bit TMR1 register RD16 -- T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module. DS39541A-page 134 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 12.0 * * * * * * * TIMER2 MODULE 12.1 Timer2 Operation The Timer2 module timer has the following features: 8-bit timer (TMR2 register) 8-bit period register (PR2) Readable and writable (both registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMR2 match of PR2 SSP module optional use of TMR2 output to generate clock shift Timer2 can be used as the PWM time-base for the PWM mode of the CCP module. The TMR2 register is readable and writable, and is cleared on any device RESET. The input clock (FOSC/4) has a prescale option of 1:1, 1:4, or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON register). The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit TMR2IF, PIR registers). The prescaler and postscaler counters are cleared when any of the following occurs: * A write to the TMR2 register * A write to the T2CON register * Any device RESET (Power-on Reset, MCLR Reset, or Watchdog Timer Reset) TMR2 is not cleared when T2CON is written. Note: Timer2 is disabled on POR. Register 12-1 shows the Timer2 Control register. Timer2 can be shut-off by clearing control bit TMR2ON (T2CON register), to minimize power consumption. Figure 12-1 is a simplified block diagram of the Timer2 module. The prescaler and postscaler selection of Timer2 are controlled by this register. REGISTER 12-1: T2CON REGISTER U-0 -- bit 7 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 0 TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 6-3 Unimplemented: Read as '0' TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale * * * 1111 = 1:16 Postscale TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 2 bit 1-0 2001 Microchip Technology Inc. Advance Information DS39541A-page 135 PIC18C601/801 12.2 Timer2 Interrupt 12.3 Output of TMR2 The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon RESET. The output of TMR2 (before the postscaler) is a clock input to the Synchronous Serial Port module, which optionally uses it to generate the shift clock. FIGURE 12-1: TIMER2 BLOCK DIAGRAM TMR2 Output(1) Sets Flag bit TMR2IF FOSC/4 Prescaler 1:1, 1:4, 1:16 2 T2CKPS1:T2CKPS0 TMR2 RESET Comparator EQ PR2 Postscaler 1:1 to 1:16 4 TOUTPS3:TOUTPS0 Note 1: TMR2 register output can be software selected by the SSP Module as a baud clock. TABLE 12-1: Name INTCON PIR1 PIE1 IPR1 TMR2 T2CON PR2 Bit 7 GIE/ GIEH -- -- -- -- REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Bit 6 PEIE/ GIEL ADIF ADIE ADIP Bit 5 TMR0IE RCIF RCIE RCIP Bit 4 INT0IE TXIF TXIE TXIP Bit 3 RBIE SSPIF SSPIE SSPIP Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP Value on POR, BOR Value on all other RESETS 0000 000x 0000 000u -000 0000 -000 0000 -000 0000 -000 0000 -000 0000 -000 0000 0000 0000 0000 0000 Timer2 Module's Register TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON Timer2 Period Register T2CKPS1 T2CKPS0 -000 0000 -000 0000 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer2 module. DS39541A-page 136 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 13.0 TIMER3 MODULE Figure 13-1 is a simplified block diagram of the Timer3 module. Register 13-1 shows the Timer3 Control register. This register controls the operating mode of the Timer3 module and sets the CCP clock source. Register 11-1 shows the Timer1 Control register. This register controls the operating mode of the Timer1 module, as well as contains the Timer1 oscillator enable bit (T1OSCEN), which can be a clock source for Timer3. Note: Timer3 is disabled on POR. The Timer3 module timer/counter has the following features: * 16-bit timer/counter (Two 8-bit registers: TMR3H and TMR3L) * Readable and writable (both registers) * Internal or external clock select * Interrupt on overflow from FFFFh to 0000h * RESET from CCP module trigger REGISTER 13-1: T3CON REGISTER R/W-0 RD16 bit 7 R/W-0 T3CCP2 R/W-0 T3CKPS1 R/W-0 T3CKPS0 R/W-0 T3CCP1 R/W-0 T3SYNC R/W-0 TMR3CS R/W-0 TMR3ON bit 0 bit 7 RD16: 16-bit Read/Write Mode Enable 1 = Enables register Read/Write of Timer3 in one 16-bit operation 0 = Enables register Read/Write of Timer3 in two 8-bit operations T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits 1x = Timer3 is the clock source for compare/capture CCP modules 01 = Timer3 is the clock source for compare/capture of CCP2, Timer1 is the clock source for compare/capture of CCP1 00 = Timer1 is the clock source for compare/capture CCP modules T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value T3SYNC: Timer3 External Clock Input Synchronization Control bit (Not usable if the system clock comes from Timer1/Timer3) When TMR3CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR3CS = 0: This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0. TMR3CS: Timer3 Clock Source Select bit 1 = External clock input from Timer1 oscillator or T1CKI (on the rising edge after the first falling edge) 0 = Internal clock (FOSC/4) TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 6,3 bit 5-4 bit 2 bit 1 bit 0 2001 Microchip Technology Inc. Advance Information DS39541A-page 137 PIC18C601/801 13.1 Timer3 Operation Timer3 can operate in one of these modes: * As a timer * As a synchronous counter * As an asynchronous counter The operating mode is determined by the clock select bit, TMR3CS (T3CON register). When TMR3CS = 0, Timer3 increments every instruction cycle. When TMR3CS = 1, Timer3 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is ignored. Timer3 also has an internal "RESET input". This RESET can be generated by the CCP module (Section 13.0). FIGURE 13-1: TIMER3 BLOCK DIAGRAM TMR3IF Overflow Interrupt Flag bit TMR3H CCP Special Trigger T3CCPx 0 CLR TMR3L TMR3ON On/Off 1 T3SYNC Prescaler 1, 2, 4, 8 0 2 TMR3CS T3CKPS1:T3CKPS0 SLEEP Input Synchronize det Synchronized Clock Input T1OSO/ T13CKI T1OSC (3) 1 T1OSCEN FOSC/4 Enable Internal Oscillator(1) Clock T1OSI Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain. FIGURE 13-2: TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE Data Bus<7:0> 8 TMR3H 8 Write TMR3L Read TMR3L TMR3IF Overflow Interrupt Flag bit 8 TMR3H TMR3 TMR3L CLR 1 To Timer1 Clock Input T1OSO/ T13CKI T1OSC 1 T1OSCEN Enable Oscillator(1) FOSC/4 Internal Clock Prescaler 1, 2, 4, 8 0 2 T3CKPS1:T3CKPS0 TMR3CS SLEEP Input TMR3ON On/Off T3SYNC Synchronize det CCP Special Trigger T3CCPx 0 Synchronized Clock Input 8 T1OSI Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain. DS39541A-page 138 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 13.2 Timer1 Oscillator 13.4 The Timer1 oscillator may be used as the clock source for Timer3. The Timer1 oscillator is enabled by setting the T1OSCEN bit (T1CON Register). The oscillator is a low power oscillator rated up to 200 kHz. Refer to "Timer1 Module", Section 11.0, for Timer1 oscillator details. Resetting Timer3 Using a CCP Trigger Output If the CCP module is configured in Compare mode to generate a "special event trigger" (CCP1M3:CCP1M0 = 1011), this signal will reset Timer3. Note: The special event triggers from the CCP module will not set interrupt flag bit TMR3IF (PIR registers). 13.3 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR3 interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit TMR3IF (PIE registers). This interrupt can be enabled/disabled by setting/clearing TMR3 interrupt enable bit TMR3IE (PIE registers). Timer3 must be configured for either Timer, or Synchronized Counter mode, to take advantage of this feature. If Timer3 is running in Asynchronous Counter mode, this RESET operation may not work. In the event that a write to Timer3 coincides with a special event trigger from CCP1, the write will take precedence. In this mode of operation, the CCPR1H:CCPR1L registers pair becomes the period register for Timer3. Refer to Section 14.0, "Capture/Compare/PWM (CCP) Modules", for CCP details. TABLE 13-1: Name INTCON PIR2 PIE2 IPR2 TMR3L TMR3H T1CON T3CON Legend: Bit 7 GIE/ GIEH -- -- -- REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER Bit 6 PEIE/ GIEL -- -- -- Bit 5 TMR0IE -- -- -- Bit 4 INT0IE -- -- -- Bit 3 RBIE BCLIF BCLIE BCLIP Bit 2 TMR0IF LVDIF LVDIE LVDIP Bit 1 INT0IF TMR3IF TMR3IE TMR3IP Bit 0 RBIF CCP2IF CCP2IE CCP2IP Value on POR, BOR 0000 000x ---- 0000 ---- 0000 ---- 0000 xxxx xxxx xxxx xxxx Value on all other RESETS 0000 000u -0-- 0000 -0-- 0000 -0-- 0000 uuuu uuuu uuuu uuuu u-uu uuuu uuuu uuuu Holding register for the Least Significant Byte of the 16-bit TMR3 register Holding register for the Most Significant Byte of the 16-bit TMR3 register RD16 RD16 -- T1CKPS1 T1CKPS0 T1OSCEN T3CCP1 T1SYNC T3SYNC T3CCP2 T3CKPS1 T3CKPS0 TMR1CS TMR1ON 0-00 0000 TMR3CS TMR3ON 0000 0000 x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer3 module. 2001 Microchip Technology Inc. Advance Information DS39541A-page 139 PIC18C601/801 NOTES: DS39541A-page 140 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 14.0 CAPTURE/COMPARE/PWM (CCP) MODULES The operation of CCP1 is identical to that of CCP2, with the exception of the special event trigger. Therefore, operation of a CCP module in the following sections is described, with respect to CCP1. Table 14-2 shows the interaction of the CCP modules. Register 14-1 shows the CCPx Control registers (CCPxCON). For the CCP1 module, the register is called CCP1CON and for the CCP2 module, the register is called CCP2CON. Each CCP (Capture/Compare/PWM) module contains a 16-bit register that can operate as a 16-bit capture register, as a 16-bit compare register, or as a PWM Duty Cycle register. Table 14-1 shows the timer resources of the CCP module modes. REGISTER 14-1: CCP1CON REGISTER CCP2CON REGISTER U-0 U-0 -- U-0 -- R/W-0 DC1B1 R/W-0 DC2B1 R/W-0 DC1B0 R/W-0 DC2B0 R/W-0 CCP1M3 R/W-0 CCP2M3 R/W-0 CCP1M2 R/W-0 CCP2M2 R/W-0 CCP1M1 R/W-0 CCP2M1 R/W-0 CCP1M0 bit 0 R/W-0 CCP2M0 bit 0 -- bit 7 U-0 CCP1CON CCP2CON -- bit 7 bit 7-6 bit 5-4 Unimplemented: Read as '0' DCxB1:DCxB0: PWM Duty Cycle bit1 and bit0 Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs (bit1 and bit0) of the 10-bit PWM duty cycle. The upper eight bits (DCx9:DCx2) of the duty cycle are found in CCPRxL. CCPxM3:CCPxM0: CCPx Mode Select bits 0000 = Capture/Compare/PWM off (resets CCPx module) 0001 = Reserved 0010 = Compare mode, toggle output on match (CCPxIF bit is set) 0011 = Reserved 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, Initialize CCP pin Low, on compare match force CCP pin High (CCPIF bit is set) 1001 = Compare mode, Initialize CCP pin High, on compare match force CCP pin Low (CCPIF bit is set) 1010 = Compare mode, Generate software interrupt on compare match (CCPIF bit is set, CCP pin is unaffected) 1011 = Compare mode, Trigger special event (CCPIF bit is set, reset TMR1 or TMR3) 11xx = PWM mode Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 3-0 2001 Microchip Technology Inc. Advance Information DS39541A-page 141 PIC18C601/801 14.1 CCP1 Module 14.3 Capture Mode Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. All are readable and writable. In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 or TMR3 registers, when an event occurs on pin RC2/CCP1. An event is defined as: * * * * every falling edge every rising edge every 4th rising edge every 16th rising edge 14.2 CCP2 Module Capture/Compare/PWM Register2 (CCPR2) is comprised of two 8-bit registers: CCPR2L (low byte) and CCPR2H (high byte). The CCP2CON register controls the operation of CCP2. All are readable and writable. TABLE 14-1: CCP MODE - TIMER RESOURCE Timer Resource Timer1 or Timer3 Timer1 or Timer3 Timer2 An event is selected by control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture is made, the interrupt request flag bit CCP1IF (PIR registers) is set. It must be cleared in software. If another capture occurs before the value in register CCPR1 is read, the old captured value will be lost. CCP Mode Capture Compare PWM 14.3.1 CCP PIN CONFIGURATION In Capture mode, the RC2/CCP1 pin should be configured as an input by setting the TRISC<2> bit. Note: If the RC2/CCP1 is configured as an output, a write to the port can cause a capture condition. 14.3.2 TIMER1/TIMER3 MODE SELECTION The timers used with the capture feature (either Timer1 and/or Timer3) must be running in Timer mode or Synchronized Counter mode. In Asynchronous Counter mode, the capture operation may not work. The timer used with each CCP module is selected in the T3CON register. TABLE 14-2: INTERACTION OF TWO CCP MODULES Interaction TMR1 or TMR3 time-base. Time-base can be different for each CCP. The compare could be configured for the special event trigger, which clears either TMR1 or TMR3, depending upon which time-base is used. The compare(s) could be configured for the special event trigger, which clears TMR1 or TMR3, depending upon which time-base is used. The PWMs will have the same frequency and update rate (TMR2 interrupt). None. None. CCPx Mode CCPy Mode Capture Capture Compare PWM PWM PWM Capture Compare Compare PWM Capture Compare DS39541A-page 142 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 14.3.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCP1IE (PIE registers) clear to avoid false interrupts and should clear the flag bit CCP1IF, following any such change in operating mode. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared; therefore, the first capture may be from a non-zero prescaler. Example 14-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the "false" interrupt. 14.3.4 CCP PRESCALER EXAMPLE 14-1: CLRF MOVLW There are four prescaler settings, specified by bits CCP1M3:CCP1M0. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. This means that any RESET will clear the prescaler counter. CHANGING BETWEEN CAPTURE PRESCALERS MOVWF CCP1CON, F ; Turn CCP module off NEW_CAPT_PS ; Load WREG with the ; new prescaler mode ; value and CCP ON CCP1CON ; Load CCP1CON with ; this value FIGURE 14-1: RC2/CCP1 pin CAPTURE MODE OPERATION BLOCK DIAGRAM TMR3H Set Flag bit CCP1IF Prescaler / 1, 4, 16 T3CCP2 TMR3 Enable CCPR1H and edge detect TMR1 Enable TMR1H CCP1M3:CCP1M0 Q's Set Flag bit CCP2IF T3CCP1 T3CCP2 Prescaler / 1, 4, 16 TMR3H TMR3 Enable CCPR2H and edge detect TMR1 Enable T3CCP2 T3CCP1 TMR1H TMR1L CCPR2L TMR3L TMR1L CCPR1L TMR3L RXB0IF or RXB1IF CCP1CON<3:0> T3CCP2 RC1/CCP2 pin CCP2M3:CCP2M0 Q's Note: I/O pins have diode protection to VDD and VSS. 2001 Microchip Technology Inc. Advance Information DS39541A-page 143 PIC18C601/801 14.4 Compare Mode 14.4.2 TIMER1/TIMER3 MODE SELECTION In Compare mode, the 16-bit CCPR1 (CCPR2) register value is constantly compared against either the TMR1 register pair value, or the TMR3 register pair value. When a match occurs, the RC2/CCP1 (RC1/CCP2) pin can have one of the following actions: * * * * Driven high Driven low Toggle output (high to low or low to high) Remains unchanged Timer1 and/or Timer3 must be running in Timer mode, or Synchronized Counter mode, if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. 14.4.3 SOFTWARE INTERRUPT MODE When Generate Software Interrupt is chosen, the CCP1 pin is not affected. Only a CCP interrupt is generated (if enabled). The action on the pin is based on the value of control bits CCP1M3:CCP1M0 (CCP2M3:CCP2M0). At the same time, interrupt flag bit CCP1IF (CCP2IF) is set. 14.4.4 SPECIAL EVENT TRIGGER In this mode, an internal hardware trigger is generated, which may be used to initiate an action. The special event trigger output of CCP1 resets the TMR1 register pair. This allows the CCPR1 register to effectively be a 16-bit programmable period register for Timer1. The special trigger output of CCPx resets either the TMR1, or TMR3 register pair. Additionally, the CCP2 Special Event Trigger will start an A/D conversion, if the A/D module is enabled. Note: The special event trigger from the CCP2 module will not set the Timer1 or Timer3 interrupt flag bits. 14.4.1 CCP PIN CONFIGURATION The user must configure the CCPx pin as an output by clearing the appropriate TRISC bit. Note: Clearing the CCP1CON register will force the RC2/CCP1 compare output latch to the default low level. This is not the data latch. FIGURE 14-2: COMPARE MODE OPERATION BLOCK DIAGRAM Special Event Trigger will: Reset Timer1 or Timer3 (but not set Timer1 or Timer3 Interrupt Flag bit) Set bit GO/DONE, which starts an A/D conversion (CCP2 only) Special Event Trigger Set Flag bit CCP1IF CCPR1H CCPR1L Q RC2/CCP1 pin TRISC<2> Output Enable S R Output Logic Comparator Match CCP1M3:CCP1M0 Mode Select T3CCP2 0 1 TMR1H Special Event Trigger TMR1L TMR3H TMR3L Set Flag bit CCP2IF T3CCP1 T3CCP2 0 1 Q RC1/CCP2 pin TRISC<1> Output Enable S R Output Logic Match Comparator CCPR2H CCPR2L CCP2M3:CCP2M0 Mode Select Note: I/O pins have diode protection to VDD and VSS. DS39541A-page 144 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 TABLE 14-3: Name INTCON PIR1 PIE1 IPR1 TRISC TMR1L TMR1H T1CON CCPR1L CCPR1H CCP1CON CCPR2L CCPR2H CCP2CON PIR2 PIE2 IPR2 TMR3L TMR3H T3CON Legend: RD16 REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Bit 6 PEIE/ GIEL ADIF ADIE ADIP Bit 5 TMR0IE RCIF RCIE RCIP Bit 4 INT0IE TXIF TXIE TXIP Bit 3 RBIE SSPIF SSPIE SSPIP Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP Value on POR, BOR Value on all other RESETS Bit 7 GIE/ GIEH -- -- -- 0000 000x 0000 000u -000 0000 -000 0000 -000 0000 -000 0000 -000 0000 -000 0000 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu PORTC Data Direction Register Holding register for the Least Significant Byte of the 16-bit TMR1 Register Holding register for the Most Significant Byte of the 16-bit TMR1 Register RD16 -- T1CKPS1 T1CKPS0 T1OSCEN Capture/Compare/PWM Register1 (LSB) Capture/Compare/PWM Register1 (MSB) -- -- DC1B1 DC1B0 CCP1M3 Capture/Compare/PWM Register2 (LSB) Capture/Compare/PWM Register2 (MSB) -- -- -- -- -- -- -- -- DC2B1 -- -- -- DC2B0 -- -- -- CCP2M3 BCLIF BCLIE BCLIP LVDIF LVDIE LVDIP TMR3IF TMR3IE TMR3IP CCP2IF CCP2IE CCP2IP T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 ---- 0000 ---- 0000 ---- 0000 ---- 0000 ---- 0000 ---- 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu Holding register for the Least Significant Byte of the 16-bit TMR3 register Holding register for the Most Significant Byte of the 16-bit TMR3 register T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1. 2001 Microchip Technology Inc. Advance Information DS39541A-page 145 PIC18C601/801 14.5 PWM Mode 14.5.1 PWM PERIOD In Pulse Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch. The PWM period is specified by writing to the PR2 register. The PWM period can be calculated by the formula: PWM period = [(PR2) + 1] * 4 * TOSC * (TMR2 prescale value) where PWM frequency is defined as 1 / [PWM period]. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: * TMR2 is cleared * The CCP1 pin is set (exception: if PWM duty cycle = 0%, the CCP1 pin will not be set) * The PWM duty cycle is latched from CCPR1L into CCPR1H Note: The Timer2 postscaler (see Section 12.1) is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. Figure 14-3 shows a simplified block diagram of the CCP module in PWM mode. For a step-by-step procedure on how to setup the CCP module for PWM operation, see Section 14.5.3. FIGURE 14-3: SIMPLIFIED PWM BLOCK DIAGRAM CCP1CON<5:4> Duty Cycle Registers CCPR1L (Master) 14.5.2 PWM DUTY CYCLE CCPR1H (Slave) Q RC2/CCP1 TMR2 (Note 1) S TRISC<2> Clear Timer, CCP1 pin and latch D.C. Comparator R The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The following equation is used to calculate the PWM duty cycle in time: PWM duty cycle = (CCPR1L:CCP1CON<5:4>) * TOSC * (TMR2 prescale value) Comparator PR2 Note 1: 8-bit timer is concatenated with 2-bit internal Q clock, or 2 bits of the prescaler, to create 10-bit time-base. CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register. The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by the equation: FOSC log --------------- FPWM PWM Resolution (max) = -----------------------------bits log ( 2 ) A PWM output (Figure 14-4) has a time-base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period). FIGURE 14-4: Period PWM OUTPUT Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2 Note: If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared. DS39541A-page 146 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 14.5.3 SETUP FOR PWM OPERATION 3. 4. 5. The following steps should be taken when configuring the CCP module for PWM operation: 1. 2. Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. Make the CCP1 pin an output by clearing the TRISC<2> bit. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. Configure the CCP1 module for PWM operation. TABLE 14-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 25 MHz 1.53 kHz 16 0FFh 10 6.10 kHz 4 FFh 10 24.41 kHz 1 FFh 10 97.66kHz 1 3Fh 8 195.31 kHz 260.42 kHz 1 1Fh 7 1 17h 6.6 PWM Frequency Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits) TABLE 14-5: Name INTCON PIR1 PIE1 IPR1 TRISC TMR2 PR2 T2CON CCPR1L CCP1CON CCPR2L CCP2CON PIR2 PIE2 IPR2 Legend: Bit 7 REGISTERS ASSOCIATED WITH PWM AND TIMER2 Bit 6 PEIE/ GIEL ADIF ADIE ADIP Bit 5 TMR0IE RCIF RCIE RCIP Bit 4 INT0IE TXIF TXIE TXIP Bit 3 RBIE SSPIF SSPIE SSPIP Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP Value on POR, BOR Value on all other RESETS GIE/ GIEH -- -- -- 0000 000x 0000 000u -000 0000 -000 0000 -000 0000 -000 0000 -000 0000 -000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu PORTC Data Direction Register Timer2 Module's Register Timer2 Module's Period Register -- Capture/Compare/PWM Register1 (LSB) -- -- DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 CCPR1H Capture/Compare/PWM Register1 (MSB) Capture/Compare/PWM Register2 (LSB) -- -- -- -- -- -- -- -- DC2B1 -- -- -- DC2B0 -- -- -- CCP2M3 BCLIF BCLIE BCLIP CCP2M2 CCP2M1 LVDIF LVDIE LVDIP TMR3IF TMR3IE TMR3IP CCP2M0 CCP2IF CCP2IE CCP2IP --00 0000 --00 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu --00 0000 --00 0000 ---- 0000 ---- 0000 ---- 0000 ---- 0000 ---- 0000 ---- 0000 CCPR2H Capture/Compare/PWM Register2 (MSB) x = unknown, u = unchanged, -- = unimplemented, read as '0'. Shaded cells are not used by PWM and Timer2. 2001 Microchip Technology Inc. Advance Information DS39541A-page 147 PIC18C601/801 NOTES: DS39541A-page 148 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 15.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE Master SSP (MSSP) Module Overview 15.1 The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module can operate in one of two modes: * Serial Peripheral InterfaceTM (SPI) * Inter-Integrated CircuitTM (I2C) - Full Master mode - Slave mode (with general address call) The I2C interface supports the following modes in hardware: * Master mode * Multi-Master mode * Slave mode 2001 Microchip Technology Inc. Advance Information DS39541A-page 149 PIC18C601/801 15.2 Control Registers The MSSP module has three associated registers. These include a status register and two control registers. Register 15-1 shows the MSSP Status Register (SSPSTAT), Register 15-2 shows the MSSP Control Register 1 (SSPCON1), and Register 15-3 shows the MSSP Control Register 2 (SSPCON2). REGISTER 15-1: SSPSTAT REGISTER R/W-0 SMP bit 7 R/W-0 CKE R-0 D/A R-0 P R-0 S R-0 R/W R-0 UA R-0 BF bit 0 bit 7 SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode In I2 C Master or Slave mode: 1= Slew rate control disabled for standard speed mode (100 kHz and 1 MHz) 0= Slew rate control enabled for high speed mode (400 kHz) CKE: SPI Clock Edge Select CKP = 0: 1 = Data transmitted on rising edge of SCK 0 = Data transmitted on falling edge of SCK CKP = 1: 1 = Data transmitted on falling edge of SCK 0 = Data transmitted on rising edge of SCK D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address P: STOP bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a STOP bit has been detected last (this bit is '0' on RESET) 0 = STOP bit was not detected last S: START bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a START bit has been detected last (this bit is '0' on RESET) 0 = START bit was not detected last R/W: Read/Write bit Information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next START bit, STOP bit, or not ACK bit. In I2 C Slave mode: 1 = Read 0 = Write In I2 C Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress. OR-ing this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is in IDLE mode. UA: Update Address (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated BF: Buffer Full Status bit Receive (SPI and I2 C modes): 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I2 C mode only): 1 = Data transmit in progress (does not include the ACK and STOP bits), SSPBUF is full 0 = Data transmit complete (does not include the ACK and STOP bits), SSPBUF is empty Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS39541A-page 150 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 REGISTER 15-2: SSPCON1 REGISTER R/W-0 WCOL bit 7 bit 7 R/W-0 SSPOV R/W-0 SSPEN R/W-0 CKP R/W-0 SSPM3 R/W-0 SSPM2 R/W-0 SSPM1 R/W-0 SSPM0 bit 0 WCOL: Write Collision Detect bit Master mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started 0 = No collision Slave mode: 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision SSPOV: Receive Overflow Indicator bit In SPI mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. (Must be cleared in software.) 0 = No overflow In I2 C mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don't care" in Transmit mode. (Must be cleared in software.) 0 = No overflow SSPEN: Synchronous Serial Port Enable bit In both modes, when enabled, these pins must be properly configured as input or output. In SPI mode: 1 = Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial port pins 0 = Disables serial port and configures these pins as I/O port pins In I2 C mode: 1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins 0 = Disables serial port and configures these pins as I/O port pins CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I2 C Slave mode: SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) In I2 C Master mode: Unused in this mode SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 0000 = SPI Master mode, clock = FOSC/4 0001 = SPI Master mode, clock = FOSC/16 0010 = SPI Master mode, clock = FOSC/64 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled. 0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin. 0110 = I2C Slave mode, 7-bit address 0111 = I2C Slave mode, 10-bit address 1000 = I2C Master mode, clock = FOSC / (4 * (SSPADD+1) ) 1001 = Reserved 1010 = Reserved 1011 = I2C firmware controlled Master mode (Slave idle) 1100 = Reserved 1101 = Reserved 1110 = I2C Slave mode, 7-bit address with START and STOP bit interrupts enabled 1111 = I2C Slave mode, 10-bit address with START and STOP bit interrupts enabled Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 6 bit 5 bit 4 bit 3 - 0 2001 Microchip Technology Inc. Advance Information DS39541A-page 151 PIC18C601/801 REGISTER 15-3: SSPCON2 REGISTER R/W-0 GCEN bit 7 bit 7 GCEN: General Call Enable bit (In I2C Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled ACKSTAT: Acknowledge Status bit (In I2C Master mode only) In Master Transmit mode: 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave ACKDT: Acknowledge Data bit (In I2C Master mode only) In Master Receive mode: Value transmitted when the user initiates an Acknowledge sequence at the end of a receive 1 = Not Acknowledge 0 = Acknowledge ACKEN: Acknowledge Sequence Enable bit (In I2C Master mode only) In Master Receive mode: 1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence idle RCEN: Receive Enable bit (In I2C Master mode only) 1 = Enables Receive mode for I2C 0 = Receive idle PEN: STOP Condition Enable bit (In I2C Master mode only) SCK release control 1 = Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware. 0 = STOP condition idle RSEN: Repeated START Condition Enabled bit (In I2C Master mode only) 1 = Initiate Repeated START condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated START condition idle SEN: START Condition Enabled bit (In I2C Master mode only) 1 = Initiate START condition on SDA and SCL pins. Automatically cleared by hardware. 0 = START condition idle Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the IDLE mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). R/W-0 ACKSTAT R/W-0 ACKDT R/W-0 ACKEN R/W-0 RCEN R/W-0 PEN R/W-0 RSEN R/W-0 SEN bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown DS39541A-page 152 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 15.3 SPI Mode FIGURE 15-1: The SPI mode allows 8 bits of data to be synchronously transmitted and received, simultaneously. All four modes of SPI are supported. To accomplish communication, typically three pins are used: * Serial Data Out (SDO) - RC5/SDO * Serial Data In (SDI) - RC4/SDI/SDA * Serial Clock (SCK) - RC3/SCK/SCL/LVOIN Additionally, a fourth pin may be used when in any Slave mode of operation: * Slave Select (SS) - RA5/SS/AN4 SDI SDO bit0 MSSP BLOCK DIAGRAM (SPI MODE) Internal Data Bus Read SSPBUF reg Write SSPSR reg Shift Clock 15.3.1 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits SSPCON1<5:0> and SSPSTAT<7:6>. These control bits allow the following to be specified: * * * * Master mode (SCK is the clock output) Slave mode (SCK is the clock input) Clock polarity (Idle state of SCK) Data input sample phase (middle or end of data output time) * Clock edge (output data on rising/falling edge of SCK) * Clock rate (Master mode only) * Slave Select mode (Slave mode only) Figure 15-1 shows the block diagram of the MSSP module, when in SPI mode. SS SS Control Enable Edge Select 2 Clock Select SSPM3:SSPM0 SMP:CKE 4 TMR2 Output 2 2 Edge Select Prescaler TOSC 4, 16, 64 ( ) SCK Data to TX/RX in SSPSR TRIS bit Note: I/O pins have diode protection to VDD and VSS. 2001 Microchip Technology Inc. Advance Information DS39541A-page 153 PIC18C601/801 The MSSP consists of a transmit/receive shift register (SSPSR) and a buffer register (SSPBUF). The SSPSR shifts the data in and out of the device, MSb first. The SSPBUF holds the data that was written to the SSPSR, until the received data is ready. Once the 8 bits of data have been received, that byte is moved to the SSPBUF register. Then the buffer full detect bit, BF (SSPSTAT register), and the interrupt flag bit, SSPIF (PIR registers), are set. This double buffering of the received data (SSPBUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSPBUF register during transmission/reception of data will be ignored, and the write collision detect bit, WCOL (SSPCON1 register), will be set. User software must clear the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register completed successfully. When the application software is expecting to receive valid data, the SSPBUF should be read before the next byte of data to transfer is written to the SSPBUF. The buffer full (BF) bit (SSPSTAT register) indicates when SSPBUF has been loaded with the received data (transmission is complete). When the SSPBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSP interrupt is used to determine when the transmission/reception has completed. The SSPBUF must be read and/or written. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. Example 15-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The SSPSR is not directly readable or writable, and can only be accessed by addressing the SSPBUF register. Additionally, the MSSP status register (SSPSTAT register) indicates the various status conditions. 15.3.2 ENABLING SPI I/O To enable the serial port, SSP enable bit, SSPEN (SSPCON1 register), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSPCON registers, and then set the SSPEN bit. This configures the SDI, SDO, SCK, and SS pins as serial port pins. For the pins to behave as the serial port function, corresponding pins must have their data direction bits (in the TRIS register) appropriately programmed. That is: * SDI is automatically controlled by the SPI module * SDO must have TRISC<5> bit cleared * SCK (Master mode) must have TRISC<3> bit cleared * SCK (Slave mode) must have TRISC<3> bit set * RA5 must be configured as digital I/O using ADCON1 register * SS must have TRISA<5> bit set Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. EXAMPLE 15-1: LOADING THE SSPBUF (SSPSR) REGISTER ;Has data been received (transmit complete)? ;No ;WREG reg = contents of SSPBUF ;Save in user RAM, if data is meaningful ;W reg = contents of TXDATA ;New data to xmit LOOP BTFSS SSPSTAT, BF BRA LOOP MOVF SSPBUF, W MOVWF RXDATA MOVF TXDATA, W MOVWF SSPBUF DS39541A-page 154 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 15.3.3 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input). The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPBUF register as a normal received byte (interrupts and status bits appropriately set). This could be useful in receiver applications as a "line activity monitor" mode. The clock polarity is selected by appropriately programming the CKP bit (SSPCON1 register). This, then, would give waveforms for SPI communication as shown in Figure 15-2, Figure 15-4, and Figure 15-5, where the MSb is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: * * * * FOSC/4 (or TCY) FOSC/16 (or 4 * TCY) FOSC/64 (or 16 * TCY) Timer2 output/2 This allows a maximum data rate (at 25 MHz) of 6.25 Mbps. Figure 15-2 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPBUF is loaded with the received data is shown. FIGURE 15-2: Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO (CKE = 0) SDO (CKE = 1) SDI (SMP = 0) Input Sample (SMP = 0) SDI (SMP = 1) Input Sample (SMP = 1) SSPIF SSPSR to SSPBUF SPI MODE WAVEFORM (MASTER MODE) 4 Clock Modes bit7 bit7 bit6 bit6 bit5 bit5 bit4 bit4 bit3 bit3 bit2 bit2 bit1 bit1 bit0 bit0 bit7 bit0 bit7 bit0 Next Q4 Cycle after Q2 2001 Microchip Technology Inc. Advance Information DS39541A-page 155 PIC18C601/801 15.3.4 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times, as specified in the electrical specifications. While in SLEEP mode, the slave can transmit/receive data. When a byte is received, the device will wake-up from SLEEP. the SDO pin is no longer driven, even if in the middle of a transmitted byte, and becomes a floating output. External pull-up/pull-down resistors may be desirable, depending on the application. Note 1: When the SPI is in Slave mode with SS pin control enabled, (SSPCON<3:0> = 0100), the SPI module will reset if the SS pin is set to VDD. 2: If the SPI is used in Slave mode with CKE set, then the SS pin control must be enabled. When the SPI module resets, the bit counter is forced to 0. This can be done by either forcing the SS pin to a high level, or clearing the SSPEN bit. To emulate two-wire communication, the SDO pin can be connected to the SDI pin. When the SPI needs to operate as a receiver, the SDO pin can be configured as an input. This disables transmissions from the SDO. The SDI can always be left as an input (SDI function), since it cannot create a bus conflict. 15.3.5 SLAVE SELECT SYNCHRONIZATION The SS pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SS pin control enabled (SSPCON1<3:0> = 04h). The pin must not be driven low for the SS pin to function as an input. The data latch must be high. When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, FIGURE 15-3: SLAVE SYNCHRONIZATION WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit7 bit6 bit7 bit0 SDI (SMP = 0) Input Sample (SMP = 0) SSPIF SSPSR to SSPBUF bit0 bit7 bit7 Next Q4 Cycle after Q2 DS39541A-page 156 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 FIGURE 15-4: SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO SDI (SMP = 0) Input Sample (SMP = 0) SSPIF SSPSR to SSPBUF Next Q4 Cycle after Q2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) bit7 bit0 FIGURE 15-5: SS Required SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO SDI (SMP = 0) Input Sample (SMP = 0) SSPIF SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit0 SSPSR to SSPBUF Next Q4 Cycle after Q2 2001 Microchip Technology Inc. Advance Information DS39541A-page 157 PIC18C601/801 15.3.6 SLEEP OPERATION 15.3.8 BUS MODE COMPATIBILITY In Master mode, all module clocks are halted, and the transmission/reception will remain in that state until the device wakes from SLEEP. After the device returns to normal mode, the module will continue to transmit/ receive data. In Slave mode, the SPI transmit/receive shift register operates asynchronously to the device. This allows the device to be placed in SLEEP mode, and data to be shifted into the SPI transmit/receive shift register. When all eight bits have been received, the MSSP interrupt flag bit will be set and, if enabled, will wake the device from SLEEP. Table 15-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits. TABLE 15-1: SPI BUS MODES Control Bits State CKP 0 0 1 1 CKE 1 0 1 0 Standard SPI Mode Terminology 0, 0 0, 1 1, 0 1, 1 15.3.7 EFFECTS OF A RESET A RESET disables the MSSP module and terminates the current transfer. There is also a SMP bit that controls when the data will be sampled. TABLE 15-2: Name INTCON PIR1 PIE1 IPR1 TRISC SSPCON TRISA SSPSTAT REGISTERS ASSOCIATED WITH SPI OPERATION Bit 7 Bit 6 PEIE/ GIEL ADIF ADIE ADIP Bit 5 TMR0IE RCIF RCIE RCIP Bit 4 INT0IE TXIF TXIE TXIP Bit 3 RBIE SSPIF SSPIE SSPIP Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP Bit 1 INT0IF Bit 0 RBIF Value on POR, BOR Value on all other RESETS GIE/ GIEH -- -- -- 0000 000x 0000 000u TMR2IF TMR1IF -000 0000 -000 0000 TMR2IE TMR1IE -000 0000 -000 0000 TMR2IP TMR1IP -000 0000 -000 0000 1111 1111 1111 1111 xxxx xxxx uuuu uuuu PORTC Data Direction Register WCOL -- SMP SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register PORTA Data Direction Register CKE D/A P S R/W UA BF SSPM0 0000 0000 0000 0000 --11 1111 --11 1111 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the MSSP in SPI mode. DS39541A-page 158 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 15.4 MSSP I2 C Operation The MSSP module in I 2C mode, fully implements all master and slave functions (including general call support) and provides interrupts on START and STOP bits in hardware to determine a free bus (Multi-Master mode). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. Two pins are used for data transfer. These are the RC3/ SCK/SCL pin, which is the clock (SCL), and the RC4/ SDI/SDA pin, which is the data (SDA). The user must configure these pins as inputs or outputs through the TRISC<4:3> bits. The MSSP module functions are enabled by setting MSSP Enable bit SSPEN (SSPCON1 register). The MSSP module has these six registers for I2C operation: MSSP Control Register1 (SSPCON1) MSSP Control Register2 (SSPCON2) MSSP Status Register (SSPSTAT) Serial Receive/Transmit Buffer (SSPBUF) MSSP Shift Register (SSPSR) - Not directly accessible * MSSP Address Register (SSPADD) * * * * * The SSPCON1 register allows control of the I 2C operation. The SSPM3:SSPM0 mode selection bits (SSPCON1 register) allow one of the following I 2C modes to be selected: * * * * I2C Master mode, clock = OSC/(4*(SSPADD +1)) I 2C Slave mode (7-bit address) I 2C Slave mode (10-bit address) I 2C Slave mode (7-bit address), with START and STOP bit interrupts enabled * I 2C Slave mode (10-bit address), with START and STOP bit interrupts enabled * I 2C firmware controlled master operation, slave is idle Selection of any I 2C mode with the SSPEN bit set, forces the SCL and SDA pins to be open drain, provided these pins are programmed to inputs by setting the appropriate TRISC bits. 15.4.1 SLAVE MODE In Slave mode, the SCL and SDA pins must be configured as inputs (TRISC<4:3> set). The MSSP module will override the input state with the output data when required (slave-transmitter). When an address is matched, or the data transfer after an address match is received, the hardware automatically will generate the acknowledge (ACK) pulse and load the SSPBUF register with the received value currently in the SSPSR register. If either or both of the following conditions are true, the MSSP module will not give this ACK pulse: a) b) The buffer full bit BF (SSPCON1 register) was set before the transfer was received. The overflow bit SSPOV (SSPCON1 register) was set before the transfer was received. FIGURE 15-6: MSSP BLOCK DIAGRAM (I2C MODE) Internal Data Bus Read SSPBUF reg Shift Clock SSPSR reg Write RC3/SCK/SCL RC4/ SDI/ SDA MSb LSb In this event, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF (PIR registers) is set. The BF bit is cleared by reading the SSPBUF register, while bit SSPOV is cleared through software. Addr Match Match Detect SSPADD reg START and STOP bit Detect Set, RESET S, P bits (SSPSTAT reg) The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirement of the MSSP module, is shown in timing parameter #100 and parameter #101. Note: I/O pins have diode protection to VDD and VSS. 2001 Microchip Technology Inc. Advance Information DS39541A-page 159 PIC18C601/801 15.4.1.1 Addressing 15.4.1.2 Reception Once the MSSP module has been enabled, it waits for a START condition to occur. Following the START condition, the eight bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse. If the addresses match, and the BF and SSPOV bits are clear, the following events occur: a) b) c) d) The SSPSR register value is loaded into the SSPBUF register. The buffer full bit BF is set. An ACK pulse is generated. MSSP interrupt flag bit SSPIF (PIR registers) is set on the falling edge of the ninth SCL pulse (interrupt is generated, if enabled). When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register. When the address byte overflow condition exists, then no acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT register) is set or bit SSPOV (SSPCON1 register) is set. An MSSP interrupt is generated for each data transfer byte. Flag bit SSPIF (PIR registers) must be cleared in software. The SSPSTAT register is used to determine the status of the byte. 15.4.1.3 Transmission In 10-bit Address mode, two address bytes need to be received by the slave. The five Most Significant bits (MSb) of the first address byte, specify if this is a 10-bit address. The R/W bit (SSPSTAT register) must specify a write so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal `1111 0 A9 A8 0', where A9 and A8 are the two MSb's of the address. The sequence of events for 10-bit addressing is as follows, with steps 7- 9 for slave-transmitter: 1. 2. Receive first (high) byte of address (the SSPIF, BF and UA bits (SSPSTAT register) are set). Update the SSPADD register with second (low) byte of address (clears bit UA and releases the SCL line). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive second (low) byte of address (bits SSPIF, BF, and UA are set). Update the SSPADD register with the first (high) byte of address. If match releases SCL line, this will clear bit UA. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive repeated START condition. Receive first (high) byte of address (bits SSPIF and BF are set). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The ACK pulse will be sent on the ninth bit and pin RC3/SCK/SCL is held low. The transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then pin RC3/SCK/SCL should be enabled by setting bit CKP (SSPCON1 register). The master must monitor the SCL pin prior to asserting another clock pulse. The slave devices may be holding off the master by stretching the clock. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time (Figure 15-8). An MSSP interrupt is generated for each data transfer byte. The SSPIF bit must be cleared in software and the SSPSTAT register is used to determine the status of the byte. The SSPIF bit is set on the falling edge of the ninth clock pulse. As a slave-transmitter, the ACK pulse from the masterreceiver is latched on the rising edge of the ninth SCL input pulse. If the SDA line is high (not ACK), then the data transfer is complete. When the ACK is latched by the slave, the slave logic is reset (resets SSPSTAT register) and the slave monitors for another occurrence of the START bit. If the SDA line was low (ACK), the transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Pin RC3/SCK/SCL should be enabled by setting bit CKP. 3. 4. 5. 6. 7. 8. 9. DS39541A-page 160 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 FIGURE 15-7: SDA I 2C SLAVE MODE WAVEFORMS FOR RECEPTION (7-BIT ADDRESS) Receiving Address R/W = 0 Receiving Data Receiving Data Not ACK ACK ACK A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P SCL SSPIF Bus Master Terminates Transfer Cleared in software SSPBUF register is read BF SSPOV Bit SSPOV is set because the SSPBUF register is still full. ACK is not sent. FIGURE 15-8: I 2C SLAVE MODE WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS) R/W = 0 Receiving Address R/W = 1 A1 ACK D7 D6 D5 D4 Transmitting Data D3 D2 D1 D0 Not ACK SDA A7 A6 A5 A4 A3 A2 SCL S 1 2 Data in Sampled 3 4 5 6 7 8 9 1 SCL held low while CPU responds to SSPIF 2 3 4 5 6 7 8 9 P SSPIF BF Cleared in software SSPBUF is written in software CKP Set bit after writing to SSPBUF (the SSPBUF must be written to before the CKP bit can be set) From SSP Interrupt Service Routine 2001 Microchip Technology Inc. Advance Information DS39541A-page 161 PIC18C601/801 15.4.2 GENERAL CALL ADDRESS SUPPORT The addressing procedure for the I2C bus is such that the first byte after the START condition usually determines which device will be the slave addressed by the master. The exception is the general call address, which can address all devices. When this address is used, all devices should, in theory, respond with an Acknowledge. The general call address is one of eight addresses reserved for specific purposes by the I2C protocol. It consists of all 0's with R/W = 0. The general call address is recognized (enabled) when the General Call Enable (GCEN) bit is set (SSPCON2 register). Following a START bit detect, eight bits are shifted into the SSPSR and the address is compared against the SSPADD. It is also compared to the general call address and fixed in hardware. If the general call address matches, the SSPSR is transferred to the SSPBUF, the BF bit is set (eighth bit), and on the falling edge of the ninth bit (ACK bit), the SSPIF interrupt flag bit is set. When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the SSPBUF. The value can be used to determine if the address was device specific or a general call address. In 10-bit mode, the SSPADD is required to be updated for the second half of the address to match, and the UA bit is set (SSPSTAT register). If the general call address is sampled when the GCEN bit is set and while the slave is configured in 10-bit address mode, then the second half of the address is not necessary. The UA bit will not be set, and the slave will begin receiving data after the Acknowledge (Figure 15-9). FIGURE 15-9: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESS) Address is compared to General Call Address after ACK, set interrupt R/W = 0 ACK D7 Receiving Data D6 D5 D4 D3 D2 D1 D0 ACK SDA SCL S SSPIF BF 1 General Call Address 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 Cleared in software SSPBUF is read SSPOV '0' GCEN '1' DS39541A-page 162 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 15.4.3 MASTER MODE Master mode of operation is supported by interrupt generation on the detection of the START and STOP conditions. The STOP (P) and START (S) bits are cleared from a RESET, or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit is set, or the bus is idle, with both the S and P bits clear. In Master mode, the SCL and SDA lines are manipulated by the MSSP hardware. The following events will cause SSP Interrupt Flag bit, SSPIF, to be set (SSP Interrupt if enabled): * * * * * START condition STOP condition Data transfer byte transmitted/received Acknowledge Transmit Repeated START condition 1. 2. 3. 4. 5. 6. Assert a START condition on SDA and SCL. Assert a Repeated START condition on SDA and SCL. Write to the SSPBUF register initiating transmission of data/address. Generate a STOP condition on SDA and SCL. Configure the I2C port to receive data. Generate an Acknowledge condition at the end of a received byte of data. The MSSP module, when configured in I2C Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a START condition and immediately write the SSPBUF register to imitate transmission, before the START condition is complete. In this case, the SSPBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPBUF did not occur. Note: 15.4.4 I2C MASTER MODE SUPPORT Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON1 and by setting the SSPEN bit. Once Master mode is enabled, the user has the following six options: FIGURE 15-10: MSSP BLOCK DIAGRAM (I2C MASTER MODE) Internal Data Bus Read SSPBUF Write Baud Rate Generator Clock arbitrate/WCOL Detect (hold off clock source) DS39541A-page 163 Shift Clock SSPSR Receive Enable MSb LSb SSPM3:SSPM0 SSPADD<6:0> SDA SDA In SCL SCL In Bus Collision START bit Detect STOP bit Detect Write Collision Detect Clock Arbitration State Counter for End of XMIT/RCV Set/Reset, S, P, WCOL (SSPSTAT) Set SSPIF, BCLIF Reset ACKSTAT, PEN (SSPCON2) Note: I/O pins have diode protection to VDD and VSS. 2001 Microchip Technology Inc. Advance Information Clock Cntl START bit, STOP bit, Acknowledge Generate PIC18C601/801 15.4.4.1 I2C Master Mode Operation A typical transmit sequence would go as follows: a) The user generates a START condition by setting the START enable (SEN) bit (SSPCON2 register). SSPIF is set. The MSSP module will wait the required start time before any other operation takes place. The user loads the SSPBUF with the address to transmit. Address is shifted out the SDA pin until all eight bits are transmitted. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit (SSPCON2 register). The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. The user loads the SSPBUF with eight bits of data. Data is shifted out the SDA pin until all eight bits are transmitted. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit (SSPCON2 register). The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. The user generates a STOP condition by setting the STOP enable bit PEN (SSPCON2 register). Interrupt is generated once the STOP condition is complete. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a Repeated START condition. Since the Repeated START condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the Read/Write (R/W) bit. In this case, the R/W bit will be logic '0'. Serial data is transmitted eight bits at a time. After each byte is transmitted, an Acknowledge bit is received. START and STOP conditions are output to indicate the beginning and the end of a serial transfer. In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the R/W bit. In this case, the R/W bit will be logic '1'. Thus, the first byte transmitted is a 7-bit slave address followed by a '1' to indicate receive bit. Serial data is received via SDA, while SCL outputs the serial clock. Serial data is received eight bits at a time. After each byte is received, an Acknowledge bit is transmitted. START and STOP conditions indicate the beginning and end of transmission. The baud rate generator used for the SPI mode operation is now used to set the SCL clock frequency for either 100 kHz, 400 kHz, or 1 MHz I2C operation. The baud rate generator reload value is contained in the lower 7 bits of the SSPADD register. The baud rate generator will automatically begin counting on a write to the SSPBUF. Once the given operation is complete (i.e., transmission of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state. b) c) d) e) f) g) h) i) j) k) l) 15.4.5 I2C BAUD RATE GENERATOR In Master mode, the reload value for the BRG is located in the lower 7 bits of the SSPADD register (Figure 15-11). When the BRG is loaded with this value, the BRG counts down to 0 and stops until another reload has taken place. The BRG count is decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically. If clock arbitration is taking place, for instance, the BRG will be reloaded when the SCL pin is sampled high (Figure 15-12). FIGURE 15-11: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM3:SSPM0 SSPADD<6:0> SSPM3:SSPM0 SCL Reload Control CLKOUT Reload BRG Down Counter FOSC/4 DS39541A-page 164 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 FIGURE 15-12: SDA BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION DX DX-1 SCL allowed to transition high SCL de-asserted but slave holds SCL low (clock arbitration) SCL BRG decrements on Q2 and Q4 cycles BRG value 03h 02h 01h 00h (hold off) 03h 02h SCL is sampled high, reload takes place and BRG starts its count BRG reload 15.4.6 I2C MASTER MODE START CONDITION TIMING Note: To initiate a START condition, the user sets the START Condition Enable (SEN) bit (SSPCON2 register). If the SDA and SCL pins are sampled high, the baud rate generator is re-loaded with the contents of SSPADD<6:0> and starts its count. If SCL and SDA are both sampled high when the baud rate generator times out (TBRG), the SDA pin is driven low. The action of the SDA being driven low while SCL is high, is the START condition, and causes the S bit (SSPSTAT register) to be set. Following this, the baud rate generator is reloaded with the contents of SSPADD<6:0> and resumes its count. When the baud rate generator times out (TBRG), the SEN bit (SSPCON2 register) will be automatically cleared by hardware, the baud rate generator is suspended leaving the SDA line held low and the START condition is complete. If at the beginning of the START condition, the SDA and SCL pins are already sampled low, or if during the START condition the SCL line is sampled low before the SDA line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag BCLIF is set, the START condition is aborted, and the I2C module is reset into its IDLE state. 15.4.6.1 WCOL Status Flag If the user writes the SSPBUF when a START sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). Note: Because queueing of events is not allowed, writing to the lower 5 bits of SSPCON2 is disabled until the START condition is complete. FIGURE 15-13: FIRST START BIT TIMING Set S bit (SSPSTAT) SDA = 1, SCL = 1 At completion of START bit, Hardware clears SEN bit and sets SSPIF bit TBRG Write to SSPBUF occurs here 1st bit SDA TBRG 2nd bit Write to SEN bit occurs here TBRG SCL S TBRG 2001 Microchip Technology Inc. Advance Information DS39541A-page 165 PIC18C601/801 15.4.7 I2C MASTER MODE REPEATED START CONDITION TIMING Immediately following the SSPIF bit getting set, the user may write the SSPBUF with the 7-bit address in 7-bit mode, or the default first address in 10-bit mode. After the first eight bits are transmitted and an ACK is received, the user may then transmit an additional eight bits of address (10-bit mode) or eight bits of data (7-bit mode). 15.4.7.1 WCOL Status Flag A Repeated START condition occurs when the RSEN bit (SSPCON2 register) is programmed high and the I2C logic module is in the IDLE state. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the baud rate generator is loaded with the contents of SSPADD<5:0> and begins counting. The SDA pin is released (brought high) for one baud rate generator count (TBRG). When the baud rate generator times out, if SDA is sampled high, the SCL pin will be de-asserted (brought high). When SCL is sampled high, the baud rate generator is re-loaded with the contents of SSPADD<6:0> and begins counting. SDA and SCL must be sampled high for one TBRG. This action is then followed by assertion of the SDA pin (SDA = 0) for one TBRG, while SCL is high. Following this, the RSEN bit (SSPCON2 register) will be automatically cleared and the baud rate generator will not be reloaded, leaving the SDA pin held low. As soon as a START condition is detected on the SDA and SCL pins, the S bit (SSPSTAT register) will be set. The SSPIF bit will not be set until the baud rate generator has timed out. Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. 2: A bus collision during the Repeated START condition occurs, if: * SDA is sampled low when SCL goes from low to high. * SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data "1". If the user writes the SSPBUF when a Repeated START sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). Note: Because queueing of events is not allowed, writing of the lower 5 bits of SSPCON2 is disabled until the Repeated START condition is complete. FIGURE 15-14: REPEATED START CONDITION WAVEFORM Set S (SSPSTAT<3>) Write to SSPCON2 occurs here. SDA = 1, SCL (no change) SDA = 1, SCL = 1 At completion of START bit, hardware clear RSEN bit and set SSPIF TBRG 1st Bit SDA TBRG TBRG Falling edge of ninth clock End of Xmit Write to SSPBUF occurs here TBRG TBRG Sr = Repeated START SCL DS39541A-page 166 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 15.4.8 I2C MASTER MODE TRANSMISSION 15.4.8.2 WCOL Status Flag If the user writes the SSPBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). WCOL must be cleared in software. 15.4.8.3 ACKSTAT Status Flag Transmission of a data byte, a 7-bit address, or the other half of a 10-bit address, is accomplished by simply writing a value to the SSPBUF register. This action will set the Buffer Full bit, BF, and allow the baud rate generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted (see data hold time specification parameter 106). SCL is held low for one baud rate generator rollover count (TBRG). Data should be valid before SCL is released high (see data setup time specification parameter 107). When the SCL pin is released high, it is held that way for TBRG. The data on the SDA pin must remain stable for that duration and some hold time after the next falling edge of SCL. After the eighth bit is shifted out (the falling edge of the eighth clock), the BF bit is cleared and the master releases SDA, allowing the slave device being addressed to respond with an ACK bit during the ninth bit time, if an address match occurs, or if data was received properly. The status of ACK is written into the ACKDT bit on the falling edge of the ninth clock. If the master receives an Acknowledge, the Acknowledge Status bit, ACKSTAT, is cleared; if not, the bit is set. After the ninth clock, the SSPIF bit is set and the master clock (baud rate generator) is suspended until the next data byte is loaded into the SSPBUF, leaving SCL low and SDA unchanged (Figure 15-15). After the write to the SSPBUF, each bit of address will be shifted out on the falling edge of SCL, until all seven address bits and the R/W bit, are completed. On the falling edge of the eighth clock, the master will deassert the SDA pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDA pin to see if the address was recognized by a slave. The status of the ACK bit is loaded into the ACKSTAT status bit (SSPCON2 register). Following the falling edge of the ninth clock transmission of the address, the SSPIF is set, the BF bit is cleared and the baud rate generator is turned off, until another write to the SSPBUF takes place, holding SCL low and allowing SDA to float. In Transmit mode, the ACKSTAT bit (SSPCON2 register) is cleared when the slave has sent an Acknowledge (ACK = 0), and is set when the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 15.4.9 I2C MASTER MODE RECEPTION Master mode reception is enabled by programming the Receive Enable bit, RCEN (SSPCON2 register). Note: The MSSP module must be in an IDLE state before the RCEN bit is set, or the RCEN bit will be disregarded. The baud rate generator begins counting and on each rollover, the state of the SCL pin changes (high to low/ low to high) and data is shifted into the SSPSR. After the falling edge of the eighth clock, the RCEN bit is automatically cleared, the contents of the SSPSR are loaded into the SSPBUF, the BF bit is set, the SSPIF flag bit is set and the baud rate generator is suspended from counting, holding SCL low. The MSSP is now in IDLE state, awaiting the next command. When the buffer is read by the CPU, the BF bit is automatically cleared. The user can then send an Acknowledge bit at the end of reception, by setting the Acknowledge Sequence Enable bit ACKEN (SSPCON2 register). 15.4.9.1 BF Status Flag In receive operation, the BF bit is set when an address or data byte is loaded into SSPBUF from SSPSR. It is cleared when the SSPBUF register is read. 15.4.9.2 SSPOV Status Flag 15.4.8.1 BF Status Flag In Transmit mode, the BF bit (SSPSTAT register) is set when the CPU writes to SSPBUF, and is cleared when all eight bits are shifted out. In receive operation, the SSPOV bit is set when eight bits are received into the SSPSR and the BF bit is already set from a previous reception. 15.4.9.3 WCOL Status Flag If the user writes the SSPBUF when a receive is already in progress (i.e., SSPSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write doesn't occur). 2001 Microchip Technology Inc. Advance Information DS39541A-page 167 FIGURE 15-15: DS39541A-page 168 Write SSPCON2<0> SEN = 1 START condition begins From Slave, clear ACKSTAT bit SSPCON2<6> R/W = 0 ACK D0 A1 ACK = 0 D7 D6 D5 D4 D3 D2 D1 Transmitting Data or Second Half of 10-bit Address SEN = 0 Transmit Address to Slave A7 SSPBUF written with 7-bit address and R/W start transmit S 1 2 3 4 5 6 7 8 9 1 SCL held low while CPU responds to SSPIF Cleared in software service routine From SSP interrupt 2 3 4 5 6 7 8 9 P A6 A5 A4 A3 A2 ACKSTAT in SSPCON2 = 1 Cleared in software Cleared in software SSPBUF written SSPBUF is written in software After START condition, SEN cleared by hardware. PIC18C601/801 SDA SCL SSPIF BF I 2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) Advance Information SEN PEN 2001 Microchip Technology Inc. R/W FIGURE 15-16: Write to SSPCON2<4> to start Acknowledge sequence SDA = ACKDT (SSPCON2<5>) = 0 Master configured as a Receiver by programming SSPCON2<3>, (RCEN = 1) ACK from Slave R/W = 1 Receiving Data from Slave ACK Receiving Data from Slave RCEN cleared automatically ACK RCEN = 1 start next receive RCEN cleared automatically ACK from Master SDA = ACKDT = 0 Set ACKEN, start Acknowledge sequence SDA = ACKDT = 1 PEN bit = 1 written here 2001 Microchip Technology Inc. A1 D0 D7 D6 D5 D4 D3 D2 D1 D7 D6 D5 D4 D3 D2 D1 D0 ACK ACK is not sent Write to SSPCON2<0> (SEN = 1) Begin START condition SEN = 0 Write to SSPBUF occurs here Start XMIT Transmit Address to Slave SDA A7 A6 A5 A4 A3 A2 Bus Master terminates transfer 5 6 7 8 9 P Set SSPIF at end of receive Set SSPIF interrupt at end of Acknowledge sequence SCL S Set SSPIF interrupt at end of receive 1 5 1 2 3 4 5 1 2 3 2 3 4 8 6 7 8 9 6 7 9 4 Data shifted in on falling edge of CLK SSPIF Cleared in software Cleared in software Set SSPIF interrupt at end of Acknowledge sequence Cleared in software Cleared in software I 2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) Advance Information Last bit is shifted into SSPSR and contents are unloaded into SSPBUF SDA = 0, SCL = 1 while CPU responds to SSPIF Cleared in software Set P bit (SSPSTAT<4>) and SSPIF BF SSPOV SSPOV is set because SSPBUF is still full PIC18C601/801 DS39541A-page 169 ACKEN PIC18C601/801 15.4.10 ACKNOWLEDGE SEQUENCE TIMING 15.4.11 STOP CONDITION TIMING An Acknowledge sequence is enabled by setting the Acknowledge Sequence enable bit, ACKEN (SSPCON2 register). When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge Data bit (ACKDT) is presented on the SDA pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be cleared. If not, the user should set the ACKDT bit before starting an Acknowledge sequence. The baud rate generator then counts for one rollover period (TBRG) and the SCL pin is de-asserted (pulled high). When the SCL pin is sampled high (clock arbitration), the baud rate generator counts for TBRG. The SCL pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the baud rate generator is turned off and the MSSP module then goes into IDLE mode (Figure 15-17). 15.4.10.1 WCOL Status Flag If the user writes the SSPBUF when an Acknowledge sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). A STOP bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN (SSPCON2 register). At the end of a receive/ transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the baud rate generator is reloaded and counts down to 0. When the baud rate generator times out, the SCL pin will be brought high, and one TBRG (baud rate generator rollover count) later, the SDA pin will be de-asserted. When the SDA pin is sampled high while SCL is high, the P bit (SSPSTAT register) is set. A TBRG later, the PEN bit is cleared and the SSPIF bit is set (Figure 15-18). 15.4.11.1 WCOL Status Flag If the user writes the SSPBUF when a STOP sequence is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write doesn't occur). FIGURE 15-17: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, Write to SSPCON2 ACKEN = 1, ACKDT = 0 TBRG SDA D0 ACK TBRG ACKEN automatically cleared SCL 8 9 SSPIF Cleared in software Set SSPIF at the end of Acknowledge sequence Set SSPIF at the end of receive Note: TBRG = one baud rate generator period. Cleared in software FIGURE 15-18: STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPCON2 Set PEN Falling edge of 9th clock TBRG SCL = 1 for TBRG, followed by SDA = 1 for TBRG after SDA sampled high, P bit (SSPSTAT) is set PEN bit (SSPCON2) is cleared by hardware and the SSPIF bit is set SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to set up STOP condition Note: TBRG = one baud rate generator period. DS39541A-page 170 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 15.4.12 CLOCK ARBITRATION 15.4.13 SLEEP OPERATION Clock arbitration occurs when the master, during any receive, transmit or Repeated START/STOP condition, de-asserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the baud rate generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the baud rate generator is reloaded with the contents of SSPADD<6:0> and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count, in the event that the clock is held low by an external device (Figure 15-19). While in SLEEP mode, the I2C module can receive addresses or data, and when an address match or complete byte transfer occurs, wake the processor from SLEEP (if the MSSP interrupt is enabled). 15.4.14 EFFECT OF A RESET A RESET disables the MSSP module and terminates the current transfer. FIGURE 15-19: CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE BRG overflow, Release SCL, If SCL = 1, load BRG with SSPADD<6:0> and start count to measure high time interval BRG overflow occurs, Release SCL, Slave device holds SCL low. SCL = 1 BRG starts counting clock high interval. SCL SCL line sampled once every machine cycle (TOSC 4). Hold off BRG until SCL is sampled high. SDA TBRG TBRG TBRG 2001 Microchip Technology Inc. Advance Information DS39541A-page 171 PIC18C601/801 15.4.15 MULTI-MASTER MODE In Multi-Master mode, the interrupt generation on the detection of the START and STOP conditions allows the determination of when the bus is free. The STOP (P) and START (S) bits are cleared from a RESET, or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit (SSPSTAT register) is set, or the bus is idle, with both the S and P bits clear. When the bus is busy, enabling the SSP interrupt will generate the interrupt when the STOP condition occurs. In Multi-Master operation, the SDA line must be monitored for arbitration, to see if the signal level is the expected output level. This check is performed in hardware, with the result placed in the BCLIF bit. Arbitration can be lost in the following states: * * * * * Address transfer Data transfer A START condition A Repeated START condition An Acknowledge condition SDA is a '1' and the data sampled on the SDA pin = '0', then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag (BCLIF) and reset the I2C port to its IDLE state. (Figure 15-20). If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF bit is cleared, the SDA and SCL lines are de-asserted, and the SSPBUF can be written to. When the user services the bus collision Interrupt Service Routine, and if the I2C bus is free, the user can resume communication by asserting a START condition. If a START, Repeated START, STOP, or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDA and SCL lines are de-asserted, and the respective control bits in the SSPCON2 register are cleared. When the user services the bus collision Interrupt Service Routine, and if the I2C bus is free, the user can resume communication by asserting a START condition. The master will continue to monitor the SDA and SCL pins. If a STOP condition occurs, the SSPIF bit will be set. A write to the SSPBUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of START and STOP conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPSTAT register, or the bus is idle and the S and P bits are cleared. 15.4.16 MULTI -MASTER COMMUNICATION, BUS COLLISION, AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a '1' on SDA, by letting SDA float high and another master asserts a '0'. When the SCL pin floats high, data should be stable. If the expected data on FIGURE 15-20: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA line pulled low by another source SDA released by Master Sample SDA. While SCL is high, data doesn't match what is driven by the master. Bus collision has occurred. SDA SCL BCLIF Set bus collision interrupt (BCLIF) DS39541A-page 172 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 15.4.16.1 Bus Collision During a START Condition During a START condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the START condition (Figure 15-21). SCL is sampled low before SDA is asserted low (Figure 15-22). If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 15-23). If, however, a '1' is sampled on the SDA pin, the SDA pin is asserted low at the end of the BRG count. The baud rate generator is then reloaded and counts down to 0, and during this time, if the SCL pin is sampled as '0', a bus collision does not occur. At the end of the BRG count, the SCL pin is asserted low. Note: The reason that bus collision is not a factor during a START condition, is that no two bus masters can assert a START condition at the exact same time. Therefore, one master will always assert SDA before the other. This condition does not cause a bus collision, because the two masters must be allowed to arbitrate the first address following the START condition. If the address is the same, arbitration must be allowed to continue into the data portion, Repeated START or STOP conditions. During a START condition, both the SDA and the SCL pins are monitored. If the SDA pin is already low, or the SCL pin is already low, then all of the following occur: * the START condition is aborted; * the BCLIF flag is set, and * the MSSP module is reset to its IDLE state (Figure 15-21). The START condition begins with the SDA and SCL pins de-asserted. When the SDA pin is sampled high, the baud rate generator is loaded from SSPADD<6:0> and counts down to 0. If the SCL pin is sampled low while SDA is high, a bus collision occurs, because it is assumed that another master is attempting to drive a data '1' during the START condition. FIGURE 15-21: BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. . Set BCLIF, S bit and SSPIF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable START condition if SDA = 1, SCL=1 SEN SDA sampled low before START condition. Set BCLIF. S bit and SSPIF set because SDA = 0, SCL = 1. SSPIF and BCLIF are cleared in software. S SEN cleared automatically because of bus collision. SSP module reset into IDLE state. BCLIF SSPIF SSPIF and BCLIF are cleared in software. 2001 Microchip Technology Inc. Advance Information DS39541A-page 173 PIC18C601/801 FIGURE 15-22: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA SCL Set SEN, enable START sequence if SDA = 1, SCL = 1 SCL = 0 before SDA = 0, Bus collision occurs, set BCLIF SCL = 0 before BRG time-out, Bus collision occurs, set BCLIF SEN BCLIF Interrupt cleared in software S SSPIF '0' '0' '0' '0' FIGURE 15-23: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Less than TBRG TBRG Set SSPIF SDA SDA pulled low by other Master. Reset BRG and assert SDA. SCL S SCL pulled low after BRG Time-out Set SEN, enable START sequence if SDA = 1, SCL = 1 SEN BCLIF '0' S SSPIF SDA = 0, SCL = 1 Set SSPIF Interrupts cleared in software DS39541A-page 174 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 15.4.16.2 Bus Collision During a Repeated START Condition During a Repeated START condition, a bus collision occurs if: a) b) A low level is sampled on SDA when SCL goes from low level to high level. SCL goes low before SDA is asserted low, indicating that another master is attempting to transmit a data '1'. reloaded and begins counting. If SDA goes from high to low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time. If SCL goes from high to low before the BRG times out and SDA has not already been asserted, a bus collision occurs. In this case, another master is attempting to transmit a data '1' during the Repeated START condition (Figure 15-25). If, at the end of the BRG time-out both SCL and SDA are still high, the SDA pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated START condition is complete. When the user de-asserts SDA and the pin is allowed to float high, the BRG is loaded with SSPADD<6:0> and counts down to 0. The SCL pin is then de-asserted and when sampled high, the SDA pin is sampled. If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data '0', see Figure 15-24). If SDA is sampled high, the BRG is FIGURE 15-24: SDA BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SCL Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. RSEN BCLIF Cleared in software '0' '0' S SSPIF FIGURE 15-25: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL BCLIF SCL goes low before SDA. Set BCLIF, release SDA and SCL. Interrupt cleared in software RSEN S SSPIF '0' 2001 Microchip Technology Inc. Advance Information DS39541A-page 175 PIC18C601/801 15.4.16.3 Bus Collision During a STOP Condition Bus collision occurs during a STOP condition if: a) After the SDA pin has been de-asserted and allowed to float high, SDA is sampled low after the BRG has timed out. After the SCL pin is de-asserted, SCL is sampled low before SDA goes high. The STOP condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the baud rate generator is loaded with SSPADD<6:0> and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data '0' (Figure 15-26). If the SCL pin is sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data '0' (Figure 15-27). b) FIGURE 15-26: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA sampled low after TBRG, set BCLIF SDA SDA asserted low SCL PEN BCLIF P SSPIF '0' '0' FIGURE 15-27: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA Assert SDA SCL goes low before SDA goes high, set BCLIF SCL PEN BCLIF P SSPIF '0' '0' DS39541A-page 176 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 16.0 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART) The USART can be configured in the following modes: * Asynchronous (full duplex) * Synchronous - Master (half duplex) * Synchronous - Slave (half duplex) The SPEN (RCSTA register) and the TRISC<7> bits have to be set, and the TRISC<6> bit must be cleared, in order to configure pins RC6/TX/CK and RC7/RX/DT as the Universal Synchronous Asynchronous Receiver Transmitter. Register 16-1 shows the Transmit Status and Control Register (TXSTA) and Register 16-2 shows the Receive Status and Control Register (RCSTA). The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of the two serial I/O modules. (USART is also known as a Serial Communications Interface or SCI.) The USART can be configured as a full duplex asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers, or it can be configured as a half duplex synchronous system that can communicate with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs, etc. REGISTER 16-1: TXSTA REGISTER R/W-0 CSRC bit 7 R/W-0 TX9 R/W-0 TXEN R/W-0 SYNC U-0 -- R/W-0 BRGH R-1 TRMT R/W-0 TX9D bit 0 bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don't care Synchronous mode: 1 = Master mode (Clock generated internally from BRG) 0 = Slave mode (Clock from external source) TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled SREN/CREN overrides TXEN in SYNC mode. SYNC: USART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode Unimplemented: Read as '0' BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full TX9D: 9th bit of Transmit Data. Can be Address/Data bit or a parity bit. Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2001 Microchip Technology Inc. Advance Information DS39541A-page 177 PIC18C601/801 REGISTER 16-2: RCSTA REGISTER R/W-0 SPEN bit 7 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (Configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception SREN: Single Receive Enable bit Asynchronous mode: Don't care Synchronous mode - Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - Slave: Unused in this mode CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables continuous receive 0 = Disables continuous receive Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enable interrupt and load of the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received, and ninth bit can be used as parity bit FERR: Framing Error bit 1 = Framing error (Can be updated by reading RCREG register and receive next valid byte) 0 = No framing error OERR: Overrun Error bit 1 = Overrun error (Can be cleared by clearing bit CREN) 0 = No overrun error RX9D: 9th bit of Received Data. Can be Address/Data bit or a parity bit. Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-0 RX9 R/W-0 SREN R/W-0 CREN R/W-0 ADDEN R-0 FERR R-0 OERR R-x RX9D bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS39541A-page 178 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 16.1 USART Baud Rate Generator (BRG) Example 16-1 shows the calculation of the baud rate error for the following conditions: FOSC = 16 MHz Desired Baud Rate = 9600 BRGH = 0 SYNC = 0 It may be advantageous to use the high baud rate (BRGH = 1), even for slower baud clocks. This is because the FOSC/(16(X + 1)) equation can reduce the baud rate error in some cases. Writing a new value to the SPBRG register causes the BRG timer to be reset (or cleared). This ensures the BRG does not wait for a timer overflow before outputting the new baud rate. The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit baud rate generator. The SPBRG register controls the period of a free running 8-bit timer. In Asynchronous mode, bit BRGH (TXSTA register) also controls the baud rate. In Synchronous mode, bit BRGH is ignored. Table 16-1 shows the formula for computation of the baud rate for different USART modes, which only apply in Master mode (internal clock). Given the desired baud rate and FOSC, the nearest integer value for the SPBRG register can be calculated using the formula in Table 16-1. From this, the error in baud rate can be determined. 16.1.1 SAMPLING The data on the RC7/RX/DT pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RX pin. EXAMPLE 16-1: Desired Baud Rate Solving for X: X X X Calculated Baud Rate Error CALCULATING BAUD RATE ERROR = FOSC / (64 (X + 1)) = = = = = = = = ( (FOSC / Desired Baud Rate) / 64 ) - 1 ((16000000 / 9600) / 64) - 1 [25.042] = 25 16000000 / (64 (25 + 1)) 9615 (Calculated Baud Rate - Desired Baud Rate) Desired Baud Rate (9615 - 9600) / 9600 0.16% TABLE 16-1: SYNC 0 1 BAUD RATE FORMULA BRGH = 0 (Low Speed) (Asynchronous) Baud Rate = FOSC/(64(X+1)) (Synchronous) Baud Rate = FOSC/(4(X+1)) BRGH = 1 (High Speed) Baud Rate = FOSC/(16(X+1)) NA Legend: X = value in SPBRG (0 to 255) TABLE 16-2: Name TXSTA RCSTA SPBRG REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Bit 6 TX9 RX9 Bit 5 TXEN SREN Bit 4 SYNC CREN Bit 3 -- ADDEN Bit 2 BRGH FERR Bit 1 TRMT OERR Bit 0 TX9D RX9D Value on POR, BOR 0000 -010 0000 000x 0000 0000 Bit 7 CSRC SPEN Value on all other RESETS 0000 -010 0000 000x 0000 0000 Baud Rate Generator Register Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used by the BRG. 2001 Microchip Technology Inc. Advance Information DS39541A-page 179 PIC18C601/801 TABLE 16-3: BAUD RATE (Kbps) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATES FOR SYNCHRONOUS MODE FOSC =25 MHz % ERROR +0.47 +0.16 -0.79 -3.85 FOSC = 16 MHz SPBRG value (decimal) 80 64 20 12 0 255 20 MHz % ERROR +0.16 +0.16 -1.96 0 10 MHz % ERROR +0.16 -1.36 +0.16 +4.17 0 3.579545 MHz % ERROR +0.23 -0.83 -2.90 +3.57 -0.57 92 46 11 8 2 0 255 SPBRG value (decimal) SPBRG value (decimal) 129 32 25 7 4 0 255 SPBRG value (decimal) 64 51 16 9 0 255 7.15909 MHz % ERROR +0.23 +0.23 +1.32 -1.88 -0.57 1 MHz % ERROR +0.16 +0.16 +0.16 +0.16 207 103 25 12 0 255 SPBRG value (decimal) SPBRG value (decimal) 185 92 22 18 5 0 255 5.0688 MHz % ERROR 0 0 -2.94 +1.54 32.768 kHz % ERROR +1.14 -2.48 6 0 255 SPBRG value (decimal) SPBRG value (decimal) 131 65 16 12 0 255 KBAUD NA NA NA NA NA 77.16 96.15 297.62 480.77 6250 24.41 KBAUD NA NA NA NA NA 76.92 96.15 294.12 500 5000 19.53 BAUD RATE (Kbps) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW KBAUD NA NA NA NA 19.23 76.92 95.24 307.70 500 4000 15.63 % ERROR +0.16 +0.16 -0.79 +2.56 0 - SPBRG value (decimal) 207 51 41 12 7 0 255 KBAUD NA NA NA NA 19.23 75.76 96.15 312.50 500 2500 9.77 KBAUD NA NA NA 9.62 19.24 77.82 94.20 298.35 NA 1789.80 6.99 KBAUD NA NA NA 9.60 19.20 74.54 97.48 NA NA 1267.20 4.95 FOSC = 4 MHz BAUD RATE (Kbps) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW % ERROR +0.16 +0.16 +0.16 +4.17 0 103 51 12 9 1 0 255 SPBRG value (decimal) KBAUD NA NA NA 9.62 19.23 76.92 1000 NA 500 1000 3.91 KBAUD NA NA NA 9.62 19.04 74.57 99.43 298.30 NA 894.89 3.50 KBAUD NA 1.20 2.40 9.62 19.23 NA NA NA NA 250 0.98 KBAUD 0.30 1.17 NA NA NA NA NA NA NA 8.20 0.03 DS39541A-page 180 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 TABLE 16-4: BAUD RATE (Kbps) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0) FOSC = 25 MHz % ERROR -0.15 -0.76 +1.73 +1.73 +1.73 FOSC = 16 MHz 162 40 19 4 3 0 255 SPBRG value (decimal) 20 MHz % ERROR +0.16 -1.36 +1.73 +1.73 +4.17 10 MHz % ERROR +0.16 +0.16 +1.73 +1.73 +1.73 3.579545 MHz % ERROR +0.23 -0.83 +1.32 -2.90 -2.90 46 22 5 2 0 255 SPBRG value (decimal) 129 64 15 7 1 0 255 SPBRG value (decimal) 129 32 15 3 0 0 255 7.15909 MHz % ERROR +0.23 -0.83 -2.90 -2.90 1 MHz % ERROR +0.16 +0.16 12 0 255 SPBRG value (decimal) 92 46 11 5 0 255 SPBRG value (decimal) 5.0688 MHz % ERROR 0 0 +3.13 +3.13 +3.13 32.768 kHz % ERROR 0 255 SPBRG value (decimal) 65 32 7 3 0 0 255 SPBRG value (decimal) SPBRG value (decimal) KBAUD NA NA 2.40 9.53 19.53 78.13 97.66 NA NA 390.63 1.53 KBAUD NA NA 2.40 9.47 19.53 78.13 NA 312.50 NA 312.50 1.22 BAUD RATE (Kbps) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW KBAUD NA 1.20 2.40 9.62 19.23 NA NA NA NA 250 0.98 % ERROR +0.16 +0.16 +0.16 +0.16 - SPBRG value (decimal) KBAUD NA KBAUD NA 1.20 2.38 9.32 18.64 NA NA NA NA 111.86 0.44 KBAUD NA 1.20 2.40 9.90 19.80 79.20 NA NA NA 79.20 0.31 207 103 25 12 0 255 1.20 2.40 9.77 19.53 78.13 NA NA NA 156.25 0.61 FOSC = 4 MHz BAUD RATE (Kbps) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW % ERROR -0.16 +1.67 +1.67 51 25 0 255 SPBRG value (decimal) KBAUD 0.30 1.20 2.40 NA NA NA NA NA NA 62.50 0.24 KBAUD 0.30 1.19 2.43 9.32 18.64 NA NA NA NA 55.93 0.22 KBAUD 0.30 1.20 NA NA NA NA NA NA NA 15.63 0.06 KBAUD NA NA NA NA NA NA NA NA NA 0.51 0.002 2001 Microchip Technology Inc. Advance Information DS39541A-page 181 PIC18C601/801 TABLE 16-5: BAUD RATE (Kbps) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1) FOSC = 25 MHz % ERROR -0.15 +0.47 +1.73 +1.73 +4.17 +4.17 FOSC = 16 MHz 162 80 19 15 4 2 0 255 SPBRG value (decimal) 20 MHz % ERROR +0.16 +0.16 +1.73 +0.16 +4.17 10 MHz % ERROR +0.16 -1.36 +1.73 +4.17 3.579545 MHz % ERROR +0.23 +0.23 +1.32 -2.90 -2.90 SPBRG value (decimal) 185 92 22 11 2 0 255 64 32 7 1 0 255 SPBRG value (decimal) 129 64 15 12 3 0 255 7.15909 MHz % ERROR +0.23 -0.83 +1.32 -2.90 1 MHz % ERROR +0.16 +0.16 +0.16 SPBRG value (decimal) 207 51 25 0 255 185 46 22 5 0 255 SPBRG value (decimal) 5.0688 MHz % ERROR 0 0 -2.94 +3.13 32.768 kHz % ERROR -2.48 SPBRG value (decimal) 6 0 255 131 32 16 3 0 255 SPBRG value (decimal) SPBRG value (decimal) KBAUD NA NA NA 9.59 19.30 78.13 97.66 312.50 520.83 1562.50 6.10 KBAUD NA NA NA 9.62 19.23 78.13 96.15 312.50 NA 1250 4.88 BAUD RATE (Kbps) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW KBAUD NA NA NA 9.62 19.23 76.92 100 NA 500 1000 3.91 % ERROR +0.16 +0.16 +0.16 +4.17 0 - SPBRG value (decimal) KBAUD NA KBAUD NA NA 2.41 9.52 19.45 74.57 NA NA NA 447.44 1.75 KBAUD NA NA 2.40 9.60 18.64 79.20 NA NA NA 316.80 1.24 103 51 12 9 1 0 255 NA NA 9.62 18.94 78.13 NA 312.50 NA 625 2.44 FOSC = 4 MHz BAUD RATE (Kbps) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW % ERROR +0.16 +0.16 +0.16 +0.16 SPBRG value (decimal) 207 103 25 12 0 255 KBAUD NA 1.20 2.40 9.62 19.23 NA NA NA NA 250 0.98 KBAUD NA 1.20 2.41 9.73 18.64 74.57 NA NA NA 55.93 0.22 KBAUD 0.30 1.20 2.40 NA NA NA NA NA NA 62.50 0.24 KBAUD 0.29 NA NA NA NA NA NA NA NA 2.05 0.008 DS39541A-page 182 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 16.2 USART Asynchronous Mode In this mode, data is transmitted in non-return-to-zero (NRZ) format. Data consists of one START bit, eight or nine data bits and one STOP bit. Data is transmitted in serial fashion with LSb first. An on-chip 8-bit baud rate generator can be programmed to generate the desired baud rate. The baud rate generator produces a clock, either x16 or x64 of the bit shift rate, depending on the BRGH bit (TXSTA register). USART does not automatically calculate the parity bit for the given data byte. If parity is to be transmitted, USART must be programmed to transmit nine bits and software must set/ clear ninth data bit as parity bit. Asynchronous mode is stopped during SLEEP. Asynchronous mode is selected by clearing the SYNC bit (TXSTA register). The USART Asynchronous module consists of the following important elements: * * * * Baud Rate Generator Sampling Circuit Asynchronous Transmitter Asynchronous Receiver Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG register is empty and flag bit TXIF (PIR registers) is set. This interrupt can be enabled/disabled by setting/clearing enable bit TXIE (PIE registers). Flag bit TXIF will be set, regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicated the status of the TXREG register, another bit TRMT (TXSTA register) shows the status of the TSR register. Status bit TRMT is a read only bit, which is set when the TSR register is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR register is empty. Note 1: The TSR register is not mapped in data memory, so it is not available to the user. 2: Flag bit TXIF is set when enable bit TXEN is set. Steps to follow when setting up an Asynchronous Transmission: 1. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH (Section 16.1). Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set transmit bit TX9. Can be used as address/data bit. Enable the transmission by setting bit TXEN, which will also set bit TXIF. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Load data to the TXREG register (starts transmission). 16.2.1 USART ASYNCHRONOUS TRANSMITTER 2. 3. 4. 5. 6. 7. The USART transmitter block diagram is shown in Figure 16-1. The heart of the transmitter is the Transmit (serial) Shift Register (TSR). The TSR register obtains its data from the Read/Write Transmit Buffer register (TXREG). The TXREG register is loaded with data in software. The TSR register is not loaded until the STOP bit has been transmitted from the previous load. As soon as the STOP bit is transmitted, the TSR is loaded with new data from the TXREG register (if available). FIGURE 16-1: USART TRANSMIT BLOCK DIAGRAM Data Bus TXIF TXREG Register 8 MSb (8) Interrupt TXEN Baud Rate CLK TRMT SPBRG TX9 Baud Rate Generator TX9D SPEN *** TSR Register LSb 0 Pin Buffer and Control RC6/TX/CK pin TXIE Note: I/O pins have diode protection to VDD and VSS. 2001 Microchip Technology Inc. Advance Information DS39541A-page 183 PIC18C601/801 FIGURE 16-2: Write to TXREG BRG Output (Shift Clock) RC6/TX/CK (pin) TXIF bit (Transmit Buffer Register Empty Flag) Word 1 ASYNCHRONOUS TRANSMISSION START Bit Bit 0 Bit 1 Word 1 Bit 7/8 STOP Bit TRMT bit (Transmit Shift Register Empty Flag) Word 1 Transmit Shift Reg FIGURE 16-3: Write to TXREG ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Word 1 Word 2 BRG Output (Shift Clock) RC6/TX/CK (pin) TXIF bit (Interrupt Reg. Flag) TRMT bit (Transmit Shift Reg. Empty Flag) Word 1 Transmit Shift Reg. START Bit Bit 0 Bit 1 Word 1 Bit 7/8 STOP Bit START Bit Word 2 Bit 0 Word 2 Transmit Shift Reg. Note: This timing diagram shows two consecutive transmissions. TABLE 16-6: Name REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 6 Bit 5 Bit 4 Bit 3 RBIE Bit 2 Bit 1 Bit 0 RBIF Value on POR, BOR 0000 000x -000 0000 -000 0000 -000 0000 0000 -00x 0000 0000 Bit 7 Value on all other RESETS 0000 000u -000 0000 -000 0000 -000 0000 0000 -00x 0000 0000 0000 0010 0000 0000 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE PIR1 PIE1 IPR1 RCSTA TXSTA -- -- -- SPEN CSRC ADIF ADIE ADIP RX9 TX9 RCIF RCIE RCIP SREN TXEN TXIF TXIE TXIP CREN TMR0IF INT0IF SSPIF CCP1IF TMR2IF TMR1IF SSPIE CCP1IE TMR2IE TMR1IE SSPIP CCP1IP TMR2IP TMR1IP -- FERR OERR TRMT RX9D TX9D TXREG USART Transmit Register SYNC ADDEN BRGH SPBRG Baud Rate Generator Register Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Transmission. 0000 0010 0000 0000 DS39541A-page 184 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 16.2.2 USART ASYNCHRONOUS RECEIVER 16.2.3 SETTING UP 9-BIT MODE WITH ADDRESS DETECT The receiver block diagram is shown in Figure 16-4. The data is received on the RC7/RX/DT pin and drives the data recovery block. The data recovery block is actually a high speed shifter, operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. Steps to follow when setting up an Asynchronous Reception: 1. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH (Section 16.1). Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, set enable bit RCIE. If 9-bit reception is desired, set bit RX9. Enable the reception by setting bit CREN. Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE was set. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. Read the 8-bit received data by reading the RCREG register. If any error occurred, clear the error by clearing enable bit CREN. This mode would typically be used in RS-485 systems. Steps to follow when setting up an Asynchronous Reception with Address Detect Enable: 1. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is required, set the BRGH bit. 2. Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. 3. If interrupts are required, set the RCEN bit and select the desired priority level with the RCIP bit. 4. Set the RX9 bit to enable 9-bit reception. 5. Set the ADDEN bit to enable address detect. 6. Enable reception by setting the CREN bit. 7. The RCIF bit will be set when reception is complete. The interrupt will be acknowledged if the RCIE and GIE bits are set. 8. Read the RCSTA register to determine if any error occurred during reception, as well as read bit 9 of data (if applicable). 9. Read RCREG to determine if the device is being addressed. 10. If any error occurred, clear the CREN bit. 11. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and interrupt the CPU. 2. 3. 4. 5. 6. 7. 8. 9. FIGURE 16-4: USART RECEIVE BLOCK DIAGRAM x64 Baud Rate CLK CREN SPBRG / 64 or / 16 FERR OERR MSb STOP (8) 7 RSR Register *** 1 LSb 0 START Baud Rate Generator RC7/RX/DT Pin Buffer and Control Data Recovery RX9 SPEN RX9D RCREG Register FIFO 8 Interrupt RCIF RCIE Note: I/O pins have diode protection to VDD and VSS. Data Bus 2001 Microchip Technology Inc. Advance Information DS39541A-page 185 PIC18C601/801 FIGURE 16-5: RX (pin) Rcv Shift Reg Rcv Buffer Reg Read Rcv Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. ASYNCHRONOUS RECEPTION START bit bit0 bit1 bit7/8 STOP bit START bit0 bit bit7/8 STOP bit START bit bit7/8 STOP bit Word 1 RCREG Word 2 RCREG TABLE 16-7: Name INTCON PIR1 PIE1 IPR1 RCSTA RCREG TXSTA SPBRG REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 INT0IE TXIF TXIE TXIP CREN SYNC Bit 3 RBIE SSPIF SSPIE SSPIP -- ADDEN Bit 2 TMR0IF Bit 1 INT0IF Bit 0 RBIF TMR1IF Value on POR, BOR 0000 000x -000 0000 -000 0000 -000 0000 0000 -00x 0000 0000 Value on all other RESETS 0000 000u -000 0000 -000 0000 -000 0000 0000 -00x 0000 0000 0000 0010 0000 0000 GIE/GIEH PEIE/GIEL TMR0IE -- -- -- SPEN CSRC ADIF ADIE ADIP RX9 TX9 RCIF RCIE RCIP SREN TXEN CCP1IF TMR2IF CCP1IE TMR2IE TMR1IE CCP1IP TMR2IP TMR1IP FERR BRGH OERR TRMT RX9D TX9D USART Receive Register Baud Rate Generator Register 0000 0010 0000 0000 Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception. DS39541A-page 186 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 16.3 USART Synchronous Master Mode bit TXIF (PIR registers) is set. The interrupt can be enabled/disabled by setting/clearing enable bit TXIE (PIE registers). Flag bit TXIF will be set, regardless of the state of enable bit TXIE, and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicates the status of the TXREG register, another bit TRMT (TXSTA register) shows the status of the TSR register. TRMT is a read only bit, which is set when the TSR is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR register is empty. The TSR is not mapped in data memory, so it is not available to the user. Steps to follow when setting up a Synchronous Master Transmission: 1. 2. 3. 4. 5. 6. 7. Initialize the SPBRG register for the appropriate baud rate (Section 16.1). Enable the synchronous master serial port by setting bits SYNC, SPEN, and CSRC. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set bit TX9. Enable the transmission by setting bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register. In Synchronous Master mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA register). In addition, enable bit SPEN (RCSTA register) is set, in order to configure the RC6/TX/CK and RC7/RX/DT I/O pins to CK (clock) and DT (data) lines, respectively. The Master mode indicates that the processor transmits the master clock on the CK line. The Master mode is entered by setting bit CSRC (TXSTA register). 16.3.1 USART SYNCHRONOUS MASTER TRANSMISSION The USART transmitter block diagram is shown in Figure 16-1. The heart of the transmitter is the Transmit (serial) Shift register (TSR). The shift register obtains its data from the Read/Write Transmit Buffer register (TXREG). The TXREG register is loaded with data in software. The TSR register is not loaded until the last bit has been transmitted from the previous load. As soon as the last bit is transmitted, the TSR is loaded with new data from the TXREG (if available). Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG is empty and interrupt TABLE 16-8: Name INTCON PIR1 PIE1 IPR1 RCSTA TXREG TXSTA SPBRG Bit 7 REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 6 PEIE/GIEL ADIF ADIE ADIP RX9 TX9 Bit 5 TMR0IE RCIF RCIE RCIP SREN TXEN Bit 4 INT0IE TXIF TXIE TXIP CREN SYNC Bit 3 RBIE SSPIF SSPIE SSPIP -- ADDEN Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP FERR BRGH Bit 1 INT0IF TMR2IF TMR2IE TMR2IP OERR TRMT Bit 0 RBIF TMR1IF TMR1IE TMR1IP RX9D TX9D Value on POR, BOR 0000 000x -000 0000 -000 0000 -000 0000 0000 -00x 0000 0000 0000 0010 0000 0000 Value on all other RESETS 0000 000u -000 0000 -000 0000 -000 0000 0000 -00x 0000 0000 0000 0010 0000 0000 GIE/GIEH -- -- -- SPEN CSRC USART Transmit Register Baud Rate Generator Register Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission. 2001 Microchip Technology Inc. Advance Information DS39541A-page 187 PIC18C601/801 FIGURE 16-6: SYNCHRONOUS TRANSMISSION Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 RC7/RX/DT pin RC6/TX/CK pin Write to TXREG Reg Write Word 1 Bit 0 Bit 1 Word 1 Bit 2 Bit 7 Bit 0 Bit 1 Word 2 Bit 7 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit TRMT '1' '1' TXEN bit Note: Sync Master mode; SPBRG = '0'; continuous transmission of two 8-bit words. FIGURE 16-7: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) bit0 bit1 bit2 bit6 bit7 RC7/RX/DT pin RC6/TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit DS39541A-page 188 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 16.3.2 USART SYNCHRONOUS MASTER RECEPTION 3. 4. 5. 6. Ensure bits CREN and SREN are clear. If interrupts are desired, set enable bit RCIE. If 9-bit reception is desired, set bit RX9. If a single reception is required, set bit SREN. For continuous reception, set bit CREN. 7. Interrupt flag bit RCIF will be set when reception is complete and an interrupt will be generated if the enable bit RCIE was set. 8. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREG register. 10. If any error occurred, clear the error by clearing bit CREN. Once Synchronous Master mode is selected, reception is enabled by setting either enable bit SREN (RCSTA register), or enable bit CREN (RCSTA register). Data is sampled on the RC7/RX/DT pin on the falling edge of the clock. If enable bit SREN is set, only a single word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are set, then CREN takes precedence. When setting up a Synchronous Master reception, follow these steps: 1. 2. Initialize the SPBRG register for the appropriate baud rate (Section 16.1). Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. TABLE 16-9: Name Bit 7 REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Bit 6 Bit 5 TMR0IE RCIF RCIE RCIP SREN TXEN Bit 4 INT0IE TXIF TXIE TXIP CREN SYNC Bit 3 RBIE SSPIF SSPIE SSPIP -- ADDEN Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP FERR BRGH Bit 1 INT0IF TMR2IF TMR2IE TMR2IP OERR TRMT Bit 0 RBIF TMR1IF TMR1IE TMR1IP RX9D TX9D Value on POR, BOR 0000 000x -000 0000 -000 0000 -000 0000 0000 -00x 0000 0000 0000 0010 0000 0000 Value on all other RESETS 0000 000u -000 0000 -000 0000 -000 0000 0000 -00x 0000 0000 0000 0010 0000 0000 INTCON GIE/GIEH PEIE/GIEL PIR1 PIE1 IPR1 RCSTA TXSTA SPBRG -- -- -- SPEN CSRC ADIF ADIE ADIP RX9 TX9 RCREG USART Receive Register Baud Rate Generator Register Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Reception. FIGURE 16-8: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 RC7/RX/DT pin RC6/TX/CK pin Write to bit SREN SREN bit CREN bit RCIF bit '0' bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 '0' (interrupt) Read RXREG Note: Timing diagram demonstrates SYNC Master mode with bit SREN = '1' and bit BRGH = '0'. 2001 Microchip Technology Inc. Advance Information DS39541A-page 189 PIC18C601/801 16.4 USART Synchronous Slave Mode 16.4.2 Synchronous Slave mode differs from the Master mode, in that the shift clock is supplied externally at the RC6/TX/CK pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in SLEEP mode. Slave mode is entered by clearing bit CSRC (TXSTA register). USART SYNCHRONOUS SLAVE RECEPTION The operation of the Synchronous Master and Slave modes is identical, except in the case of the SLEEP mode and bit SREN, which is a "don't care" in Slave mode. If receive is enabled by setting bit CREN prior to the SLEEP instruction, then a word may be received during SLEEP. On completely receiving the word, the RSR register will transfer the data to the RCREG register, and if enable bit RCIE bit is set, the interrupt generated will wake the chip from SLEEP. If the global interrupt is enabled, the program will branch to the interrupt vector. When setting up a Synchronous Slave Reception, follow these steps: 1. Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC. If interrupts are desired, set enable bit RCIE. If 9-bit reception is desired, set bit RX9. To enable reception, set enable bit CREN. Flag bit RCIF will be set when reception is complete. An interrupt will be generated if enable bit RCIE was set. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. Read the 8-bit received data by reading the RCREG register. If any error occurred, clear the error by clearing bit CREN. 16.4.1 USART SYNCHRONOUS SLAVE TRANSMIT The operation of the Synchronous Master and Slave modes are identical, except in the case of the SLEEP mode. If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: a) b) c) d) The first word will immediately transfer to the TSR register and transmit. The second word will remain in TXREG register. Flag bit TXIF will not be set. When the first word has been shifted out of TSR, the TXREG register will transfer the second word to the TSR and flag bit TXIF will be set. If enable bit TXIE is set, the interrupt will wake the chip from SLEEP. If the global interrupt is enabled, the program will branch to the interrupt vector. 2. 3. 4. 5. e) 6. When setting up a Synchronous Slave Transmission, follow these steps: 1. 2. 3. 4. 5. 6. 7. Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit CSRC. Clear bits CREN and SREN. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set bit TX9. Enable the transmission by setting enable bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register. 7. 8. TABLE 16-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Name INTCON PIR1 PIE1 IPR1 RCSTA TXREG TXSTA SPBRG Bit 7 Bit 6 Bit 5 Bit 4 INT0IE TXIF TXIE TXIP CREN SYNC Bit 3 RBIE SSPIF SSPIE SSPIP -- ADDEN Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP FERR BRGH Bit 1 INT0IF TMR2IF TMR2IE TMR2IP OERR TRMT Bit 0 RBIF TMR1IF TMR1IE TMR1IP RX9D TX9D Value on POR, BOR 0000 000x -000 0000 -000 0000 -000 0000 0000 -00x 0000 0000 Value on all other RESETS 0000 000u -000 0000 -000 0000 -000 0000 0000 -00x 0000 0000 0000 0010 0000 0000 GIE/GIEH PEIE/GIEL TMR0IE -- -- -- SPEN CSRC ADIF ADIE ADIP RX9 TX9 RCIF RCIE RCIP SREN TXEN USART Transmit Register Baud Rate Generator Register 0000 0010 0000 0000 Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Slave Transmission. DS39541A-page 190 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 TABLE 16-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Name INTCON PIR1 PIE1 IPR1 RCSTA RCREG TXSTA SPBRG Bit 7 Bit 6 Bit 5 Bit 4 INT0IE TXIF TXIE TXIP CREN SYNC Bit 3 RBIE SSPIF SSPIE SSPIP -- ADDEN Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP FERR BRGH Bit 1 INT0IF TMR2IF TMR2IE TMR2IP OERR TRMT Bit 0 RBIF TMR1IF TMR1IE TMR1IP RX9D TX9D Value on POR, BOR 0000 000x -000 0000 -000 0000 -000 0000 0000 -00x 0000 0000 Value on all other RESETS 0000 000u -000 0000 -000 0000 -000 0000 0000 -00x 0000 0000 0000 0010 0000 0000 GIE/GIEH PEIE/GIEL TMR0IE -- -- -- SPEN CSRC ADIF ADIE ADIP RX9 TX9 RCIF RCIE RCIP SREN TXEN USART Receive Register Baud Rate Generator Register 0000 0010 0000 0000 Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Slave Reception. 2001 Microchip Technology Inc. Advance Information DS39541A-page 191 PIC18C601/801 NOTES: DS39541A-page 192 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 17.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The A/D module has five registers: * * * * * A/D Result High Register (ADRESH) A/D Result Low Register (ADRESL) A/D Control Register 0 (ADCON0) A/D Control Register 1 (ADCON1) A/D Control Register 2 (ADCON2) The analog-to-digital (A/D) converter module has 8 inputs for the PIC18C601 devices and 12 for the PIC18C801 devices. This module has the ADCON0, ADCON1, and ADCON2 registers. The A/D allows conversion of an analog input signal to a corresponding 10-bit digital number. The ADCON0 register, shown in Register 17-1, controls the operation of the A/D module. The ADCON1 register, shown in Register 17-2, configures the functions of the port pins. The ADCON2, shown in Register 16-3, configures the A/D clock source and justification. REGISTER 17-1: ADCON0 REGISTER U-0 -- bit 7 U-0 -- R/W-0 CHS3 R/W-0 CHS2 R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE R/W-0 ADON bit 0 bit 7-6 bit 5-2 Unimplemented: Read as '0' CHS3:CHS0: Analog Channel Select bits 0000 = channel 00, (AN0) 0001 = channel 01, (AN1) 0010 = channel 02, (AN2) 0011 = channel 03, (AN3) 0100 = channel 04, (AN4) 0101 = channel 05, (AN5) 0110 = channel 06, (AN6) 0111 = channel 07, (AN7) 1000 = channel 08, (AN8)(1) 1001 = channel 09, (AN9)(1) 1010 = channel 10, (AN10)(1) 1011 = channel 11, (AN11)(1) 1100 = Reserved 1101 = Reserved 1110 = Reserved 1111 = Reserved These channels are not available on the PIC18C601 devices. GO/DONE: A/D Conversion Status bit When ADON = 1: 1 = A/D conversion in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion is complete. 0 = A/D conversion not in progress ADON: A/D On bit 1 = A/D converter module is operating 0 = A/D converter module is shut-off and consumes no operating current Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 1 bit 0 2001 Microchip Technology Inc. Advance Information DS39541A-page 193 PIC18C601/801 REGISTER 17-2: ADCON1 REGISTER U-0 -- bit 7 bit 7-6 bit 5-4 Unimplemented: Read as '0' VCFG1:VCFG0: Voltage Reference Configuration bits A/D VREF+ 00 01 10 11 bit 3-0 AVDD External VREF+ AVDD External VREF+ A/D VREFAVSS AVSS External VREFExternal VREFU-0 -- R/W-0 VCFG1 R/W-0 VCFG0 R/W-0 PCFG3 R/W-0 PCFG2 R/W-0 PCFG1 R/W-0 PCFG0 bit 0 PCFG3:PCFG0: A/D Port Configuration Control bits AN11 AN10 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 AN9 A A A A A A D D D D D D D D D D AN8 A A A A A A A D D D D D D D D D AN7 A A A A A A A A D D D D D D D D AN6 A A A A A A A A A D D D D D D D AN5 A A A A A A A A A A D D D D D D AN4 A A A A A A A A A A A D D D D D AN3 AN2 AN1 AN0 A A A A A A A A A A A A D D D D A A A A A A A A A A A A A D D D A A A A A A A A A A A A A A D D A A A A A A A A A A A A A A A D A A A A D D D D D D D D D D D D A A A A A D D D D D D D D D D D A = Analog input D = Digital I/O Shaded cells = Additional A/D channels available on PIC18C801 devices. Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown DS39541A-page 194 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 REGISTER 17-3: ADCON2 REGISTER R/W-0 ADFM bit 7 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified Unimplemented: Read as '0' ADCS2:ADCS0: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 011 = FRC (clock derived from an internal RC oscillator = 1 MHz max) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 111 = FRC (clock derived from an internal RC oscillator = 1 MHz max) Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 ADCS2 R/W-0 ADCS1 R/W-0 ADCS0 bit 0 bit 6-3 bit 2-0 The analog reference voltage is software selectable to either the device's positive and negative supply voltage (VDD and VSS), or the voltage level on the RA3/AN3/VREF+ pin and RA2/AN2/VREF-. The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode. To operate in SLEEP, the A/D conversion clock must be derived from the A/D's internal RC oscillator. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. A device RESET forces all registers to their RESET state. This forces the A/D module to be turned off and any conversion is aborted. Each port pin associated with the A/D converter can be configured as an analog input (RA3 can also be a voltage reference), or as a digital I/O. The ADRESH and ADRESL registers contain the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRESH/ADRESL registers, the GO/DONE bit (ADCON0 register) is cleared, and A/D interrupt flag bit ADIF is set. The block diagram of the A/D module is shown in Figure 17-1. 2001 Microchip Technology Inc. Advance Information DS39541A-page 195 PIC18C601/801 FIGURE 17-1: A/D BLOCK DIAGRAM CHS3:CHS0 0111 RF2/AN7 0110 RF1/AN6 0101 RF0/AN5 0100 RA5/AN4 0011 RA3/AN3/VREF+ 0010 RA2/AN2/VREF0001 RA1/AN1 VIN (Input voltage) 1011 0000 RA0/AN0 RH7/AN11(1) RH6/AN10(1) RH5/AN9(1) RH4/AN8(1) A/D Converter 1010 1001 AVDD VREF+ (Reference Voltage) VCFG0 1000 VREF(Reference Voltage) VCFG1 AVSS Note 1: These channels are not available on the PIC18C601 devices. DS39541A-page 196 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 The value in the ADRESH/ADRESL registers is not modified for a Power-on Reset. The ADRESH/ADRESL registers will contain unknown data after a Power-on Reset. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 17.1. After this acquisition time has elapsed, the A/D conversion can be started. The following steps should be followed to do an A/D conversion: 1. Configure the A/D module: * Configure analog pins, voltage reference and digital I/O (ADCON1) * Select A/D input channel (ADCON0) * Select A/D conversion clock (ADCON2) * Turn on A/D module (ADCON0) 2. Configure A/D interrupt (if desired): * Clear ADIF bit * Set ADIE bit * Set GIE bit Wait the required acquisition time. Start conversion: * Set GO/DONE bit (ADCON0 register) Wait for A/D conversion to complete, by either: * Polling for the GO/DONE bit to be cleared, OR * Waiting for the A/D interrupt Read A/D Result registers (ADRESH:ADRESL); clear bit ADIF, if required. For next conversion, go to step 1 or step 2, as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2TAD is required before next acquisition starts. 3. 4. 5. 6. 7. FIGURE 17-2: ANALOG INPUT MODEL VDD VT = 0.6 V Rs ANx RIC 1 k Sampling Switch SS RSS VAIN CPIN 5 pF VT = 0.6 V I leakage 500 nA CHOLD = 120 pF VSS Legend: CPIN = input capacitance = threshold voltage VT I LEAKAGE = leakage current at the pin due to various junctions = interconnect resistance RIC = sampling switch SS = sample/hold capacitance (from DAC) CHOLD RSS = sampling switch resistance 6V 5V VDD 4V 3V 2V 5 6 7 8 9 10 11 Sampling Switch ( k ) 2001 Microchip Technology Inc. Advance Information DS39541A-page 197 PIC18C601/801 17.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 17-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum recommended impedance for analog sources is 2.5k. After the analog input channel is selected (changed), this acquisition must be done before the conversion can be started. Note: When the conversion is started, the holding capacitor is disconnected from the input pin. To calculate the minimum acquisition time, Equation 17-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution. Example 17-1 shows the calculation of the minimum required acquisition time TACQ. This calculation is based on the following application system assumptions: CHOLD Rs Conversion Error VDD Temperature VHOLD = = = = = 120 pF 2.5 k 1/2 LSb 5V Rss = 7 k 50C (system max.) 0V @ time = 0 EQUATION 17-1: TACQ = ACQUISITION TIME Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient TAMP + TC + TCOFF = EQUATION 17-2: VHOLD or TC = = A/D MINIMUM CHARGING TIME (VREF - (VREF/2048)) * (1 - e(-Tc/CHOLD(RIC + RSS + RS))) -(120 pF)(1 k + RSS + RS) ln(1/2047) EXAMPLE 17-1: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME TACQ TACQ TC = = = TAMP + TC + TCOFF 2 s + TC + [(Temp - 25C)(0.05 s/C)] -CHOLD (RIC + RSS + RS) ln(1/2047) -120 pF (1 k + 7 k + 2.5 k) ln(0.0004885) -120 pF (10.5 k) ln(0.0004885) -1.26 s (-7.6241) 9.61 s 2 s + 9.61 s + [(50C - 25C)(0.05 s/C)] 11.61 s + 1.25 s 12.86 s Temperature coefficient is only required for temperatures > 25C. TACQ = DS39541A-page 198 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 17.2 Selecting the A/D Conversion Clock 17.3 Configuring Analog Port Pins The ADCON1, TRISA, TRISF and TRISH registers control the operation of the A/D port pins. The port pins needed as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the CHS3:CHS0 bits and the TRIS bits. Note 1: When reading the port register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs will convert an analog input. Analog levels on a digitally configured input will not affect the conversion accuracy. 2: Analog levels on any pin defined as a digital input may cause the input buffer to consume current out of the device's specification limits. The A/D conversion time per bit is defined as TAD. The A/D conversion requires 12 TAD per 10-bit conversion. The source of the A/D conversion clock is software selectable. There are seven possible options for TAD: * * * * * * * 2TOSC 4TOSC 8TOSC 16TOSC 32TOSC 64TOSC Internal RC oscillator For correct A/D conversions, the A/D conversion clock (TAD) must be selected to ensure a minimum TAD time of 1.6 s. Table 17-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected. TABLE 17-1: TAD vs. DEVICE OPERATING FREQUENCIES AD Clock Source (TAD) Maximum Device Frequency PIC18C601/801 1.25 MHz 2.50 MHz 5.00 MHz 10.0 MHz 20.0 MHz -- -- PIC18LC601/801(5) 666 kHz 1.33 MHz 2.67 MHz 5.33 MHz 10.67 MHz -- -- Operation 2TOSC 4TOSC 8TOSC 16TOSC 32TOSC 64TOSC RC Note 1: 2: 3: 4: ADCS2:ADCS0 000 100 001 101 010 110 x11 The RC source has a typical TAD time of 4 s. These values violate the minimum required TAD time. For faster conversion times, the selection of another clock source is recommended. For device frequencies above 1 MHz, the device must be in SLEEP for the entire conversion or the A/D accuracy may be out of specification. 5: This column is for the LC devices only. 2001 Microchip Technology Inc. Advance Information DS39541A-page 199 PIC18C601/801 17.4 A/D Conversions 17.5 Use of the CCP2 Trigger Figure 17-3 shows the operation of the A/D converter after the GO bit has been set. Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D result register pair will NOT be updated with the partially completed A/D conversion sample. That is, the ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers). After the A/D conversion is aborted, a 2TAD wait is required before the next acquisition is started. After this 2TAD wait, acquisition on the selected channel is automatically started. Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. An A/D conversion can be started by the "special event trigger" of the CCP2 module. This requires that the CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be programmed as 1011, and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D conversion and the Timer1 (or Timer3) counter will be reset to zero. Timer1 (or Timer3) is reset to automatically repeat the A/D acquisition period with minimal software overhead (moving ADRESH/ADRESL to the desired location). The appropriate analog input channel must be selected and the minimum acquisition done before the "special event trigger" sets the GO/DONE bit (starts a conversion). If the A/D module is not enabled (ADON is cleared), the "special event trigger" will be ignored by the A/D module, but will still reset the Timer1 (or Timer3) counter. FIGURE 17-3: A/D CONVERSION TAD CYCLES TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b9 b0 b9 b4 b2 b5 b3 b1 b6 b8 b7 Conversion Starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. DS39541A-page 200 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 TABLE 17-2: Name INTCON PIR1 PIE1 IPR1 PIR2 PIE2 IPR2 ADRESH ADRESL ADCON0 ADCON1 ADCON2 PORTA TRISA PORTF LATF TRISF PORTH(1) LATH(1) TRISH (1) SUMMARY OF A/D REGISTERS Bit 6 Bit 5 Bit 4 INT0IE TXIF TXIE TXIP -- -- -- Bit 3 RBIE SSPIF SSPIE SSPIP BCLIF BCLIE BCLIP Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP LVDIF LVDIE LVDIP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP TMR3IF TMR3IE TMR3IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP CCP2IF CCP2IE CCP2IP Value on POR, BOR 0000 000x -000 0000 -000 0000 -000 0000 -0-- 0000 ---- 0000 ---- 0000 xxxx xxxx xxxx xxxx Bit 7 GIE/GIEH -- -- -- -- -- -- Value on all other RESETS 0000 000u -000 0000 -000 0000 -000 0000 -0-- 0000 ---- 0000 ---- 0000 uuuu uuuu uuuu uuuu 0000 00-0 ---- -000 0--- -000 --0u 0000 --11 1111 u000 0000 uuuu uuuu 1111 1111 0000 xxxx uuuu uuuu 1111 1111 PEIE/GIEL TMR0IE ADIF ADIE ADIP -- -- -- RCIF RCIE RCIP -- -- -- A/D Result Register A/D Result Register -- -- ADFM -- -- RF7 LATF7 RH7 LATH7 -- -- -- -- RF6 LATF6 RH6 LATH6 CHS3 VCFG1 -- RA5 RF5 LATF5 RH5 LATH5 CHS3 -- RA4 RF4 LATF4 RH4 LATH4 CHS1 -- RA3 RF3 LATF3 RH3 LATH3 CHS0 PCFG2 ADCS2 RA2 RF2 LATF2 RH2 LATH2 GO/DONE PCFG1 ADCS1 RA1 RF1 LATF1 RH1 LATH1 ADON PCFG0 ADCS0 RA0 RF0 LATF0 RH0 LATH0 VCFG0 PCFG3 0000 00-0 ---- -000 0--- -000 --0x 0000 --11 1111 x000 0000 xxxx xxxx 1111 1111 0000 xxxx xxxx xxxx 1111 1111 PORTA Data Direction Register PORTF Data Direction Control Register PORTH Data Direction Control Register Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used for A/D conversion. Note 1: Only available on PIC18C801 devices. 2001 Microchip Technology Inc. Advance Information DS39541A-page 201 PIC18C601/801 NOTES: DS39541A-page 202 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 18.0 LOW VOLTAGE DETECT In many applications, the ability to determine if the device voltage (VDD) is below a specified voltage level is a desirable feature. A window of operation for the application can be created, where the application software can do "housekeeping tasks", before the device voltage exits the valid operating range. This can be done using the Low Voltage Detect module. This module is software programmable circuitry, where a device voltage trip point can be specified (internal reference voltage or external voltage input). When the voltage of the device becomes lower than the specified point, an interrupt flag is set. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to that interrupt source. The Low Voltage Detect circuitry is completely under software control. This allows the circuitry to be "turned off" by the software, which minimizes the current consumption for the device. Figure 18-1 shows a possible application voltage curve (typically for batteries). Over time, the device voltage decreases. When the device voltage equals voltage VA, the LVD logic generates an interrupt. This occurs at time TA. The application software then has the time, until the device voltage is no longer in valid operating range, to shut-down the system. Voltage point VB is the minimum valid operating voltage specification. This occurs at time TB. TB - TA is the total time for shut-down. Figure 18-2 shows the block diagram for the LVD module. A comparator uses an internally generated reference voltage as the set point. When the selected tap output of the device voltage crosses the set point (is lower than), the LVDIF bit (PIR registers) is set. Each node in the resister divider represents a "trip point" voltage. The "trip point" voltage is the minimum supply voltage level at which the device can operate, before the LVD module asserts an interrupt. When the supply voltage is equal to the trip point, the voltage tapped off of the resistor array (or external LVDIN input pin) is equal to the voltage generated by the internal voltage reference module. The comparator then generates an interrupt signal setting the LVDIF bit. This voltage is software programmable to any one of 16 values (see Figure 18-2). The trip point is selected by programming the LVDL3:LVDL0 bits (LVDCON<3:0>). FIGURE 18-2: VDD LOW VOLTAGE DETECT (LVD) BLOCK DIAGRAM LVD Control Register FIGURE 18-1: TYPICAL LOW VOLTAGE DETECT APPLICATION 16 to 1 MUX LVDIF Voltage VA VB LVDIN LVDEN Internally Generated Reference Voltage Time TA TB Legend: VA = LVD trip point VB = Minimum valid device operating range 2001 Microchip Technology Inc. Advance Information DS39541A-page 203 PIC18C601/801 18.1 Control Register The Low Voltage Detect Control register (Register 18-1) controls the operation of the Low Voltage Detect circuitry. REGISTER 18-1: LVDCON REGISTER U-0 -- bit 7 U-0 -- R-0 IRVST R/W-0 LVDEN R/W-0 LVDL3 R/W-1 LVDL2 R/W-0 LVDL1 R/W-1 LVDL0 bit 0 bit 7-6 bit 5 Unimplemented: Read as '0' IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the Low Voltage Detect logic will generate the interrupt flag at the specified voltage range 0 = Indicates that the Low Voltage Detect logic will not generate the interrupt flag at the specified voltage range and the LVD interrupt should not be enabled LVDEN: Low Voltage Detect Power Enable bit 1 = Enables LVD, powers up LVD circuit 0 = Disables LVD, powers down LVD circuit LVDL3:LVDL0: Low Voltage Detection Limit bits 1111 = External analog input is used (input comes from the LVDIN pin) 1110 = 4.5V 1101 = 4.2V 1100 = 4.0V - Reserved on PIC18C601/801 1011 = 3.8V - Reserved on PIC18C601/801 1010 = 3.6V - Reserved on PIC18C601/801 1001 = 3.5V - Reserved on PIC18C601/801 1000 = 3.3V - Reserved on PIC18C601/801 0111 = 3.0V - Reserved on PIC18C601/801 0110 = 2.8V - Reserved on PIC18C601/801 0101 = 2.7V - Reserved on PIC18C601/801 0100 = 2.5V - Reserved on PIC18C601/801 0011 = 2.4V - Reserved on PIC18C601/801 0010 = 2.2V - Reserved on PIC18C601/801 0001 = 2.0V - Reserved on PIC18C601/801 0000 = Reserved on PIC18C601/801 and PIC18LC801/601 LVDL3:LVDL0 modes which result in a trip point below the valid operating voltage of the device are not tested. Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 4 bit 3-0 DS39541A-page 204 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 18.2 Operation Depending on the power source for the device voltage, the voltage normally decreases relatively slowly. This means that the LVD module does not need to be constantly operating. To decrease current consumption, the LVD circuitry only needs to be enabled for short periods, where the voltage is checked. After doing the check, the LVD module may be disabled. Each time that the LVD module is enabled, the circuitry requires some time to stabilize. After the circuitry has stabilized, all status flags may be cleared. The module will then indicate the proper state of the system. The following steps are needed to setup the LVD module: 1. Write the value to the LVDL3:LVDL0 bits (LVDCON register), which selects the desired LVD trip point. Ensure that LVD interrupts are disabled (the LVDIE bit is cleared or the GIE bit is cleared). Enable the LVD module (set the LVDEN bit in the LVDCON register). Wait for the LVD module to stabilize (the IRVST bit to become set). Clear the LVD interrupt flag, which may have falsely become set, until the LVD module has stabilized (clear the LVDIF bit). Enable the LVD interrupt (set the LVDIE and the GIE bits). 2. 3. 4. 5. 6. Figure 18-3 shows typical waveforms that the LVD module may be used to detect. FIGURE 18-3: CASE 1: LOW VOLTAGE DETECT WAVEFORMS LVDIF may not be set VDD VLVD LVDIF Enable LVD Internally Generated Reference Stable 50 ms LVDIF cleared in software CASE 2: VDD VLVD LVDIF Enable LVD Internally Generated Reference Stable 50 ms LVDIF cleared in software LVDIF cleared in software, LVDIF remains set since LVD condition still exists 2001 Microchip Technology Inc. Advance Information DS39541A-page 205 PIC18C601/801 18.2.1 REFERENCE VOLTAGE SET POINT 18.3 External Analog Voltage Input The Internal Reference Voltage of the LVD module may be used by other internal circuitry (the programmable Brown-out Reset). If these circuits are disabled (lower current consumption), the reference voltage circuit requires time to become stable before a low voltage condition can be reliably detected. This time is invariant of system clock speed. This start-up time is specified in electrical specification parameter #36. The low voltage interrupt flag will not be enabled until a stable reference voltage is reached. Refer to the waveform in Figure 18-3. The LVD module has an additional feature that allows the user to supply the trip point voltage to the module from an external source (the LVDIN pin). The LVDIN pin is used as the trip point when the LVDL3:LVDL0 bits equal '1111'. This state connects the LVDIN pin voltage to the comparator. The other comparator input is connected to an internal reference voltage source. 18.4 Operation During SLEEP 18.2.2 CURRENT CONSUMPTION When the module is enabled, the LVD comparator and voltage divider are enabled and will consume static current. The voltage divider can be tapped from multiple places in the resistor array. Total current consumption, when enabled, is specified in electrical specification parameter #D022B. When enabled, the LVD circuitry continues to operate during SLEEP. If the device voltage crosses the trip point, the LVDIF bit will be set and the device will wakeup from SLEEP. Device execution will continue from the interrupt vector address, if interrupts have been globally enabled. 18.5 Effects of a RESET A device RESET forces all registers to their RESET state. This forces the LVD module to be turned off. DS39541A-page 206 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 19.0 SPECIAL FEATURES OF THE CPU while the power supply stabilizes. With these two timers on-chip, most applications need no external RESET circuitry. SLEEP mode is designed to offer a very low current Power-down mode. The user can wake-up from SLEEP through external RESET, Watchdog Timer Wake-up or through an interrupt. Several oscillator options are also available to allow the part to fit the application. The RC oscillator option saves system cost, while the LP crystal option saves power. By default, HS oscillator mode is selected. There are two main modes of operations for external memory interface: 8-bit and 16-bit (default). A set of configuration bits are used to select various options. There are several features intended to maximize system reliability, minimize cost through elimination of external components and provide power saving operating modes: * OSC Selection * RESET - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) * Interrupts * Watchdog Timer (WDT) * SLEEP * ID Locations PIC18C601/801 devices have a Watchdog Timer, which can be permanently enabled/disabled via the configuration bits, or it can be software controlled. By default, the Watchdog Timer is disabled to allow software control. It runs off its own RC oscillator for cost reduction. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in RESET until the crystal oscillator is stable. The other is the Powerup Timer (PWRT), which provides a fixed delay on power-up only, designed to keep the part in RESET 19.1 Configuration Bits The configuration bits can be programmed (read as '0'), or left unprogrammed (read as '1'), to select various device configurations. These bits are mapped starting at program memory location 300000h. The user will note that address 300000h is beyond the user program memory space. In fact, it belongs to the configuration memory space (300000h - 3FFFFFh), which can only be accessed using table reads and table writes. TABLE 19-1: File Name 300001h 300002h 300003h 300006h 3FFFFEh 3FFFFFh CONFIGURATION BITS AND DEVICE IDs Bit 7 -- -- -- r DEV2 DEV10 Bit 6 -- BW -- -- DEV1 DEV9 Bit 5 -- -- -- -- DEV0 DEV8 Bit 4 -- -- -- -- REV4 DEV7 Bit 3 -- -- -- REV3 DEV6 Bit 2 -- -- -- REV2 DEV5 Bit 1 FOSC1 -- -- REV1 DEV4 Bit 0 FOSC0 PWRTEN WDTEN STVREN REV0 DEV3 Default/ Unprogrammed Value ---- --11 -1-- ---1 ---- 1110 1--- ---1 0000 0000 0000 0000 CONFIG1H CONFIG2L CONFIG2H CONFIG4L DEVID1 DEVID2 WDTPS2 WDTPS1 WDTPS0 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, maintain `1'. Shaded cells are unimplemented, read as '0'. 2001 Microchip Technology Inc. Advance Information DS39541A-page 207 PIC18C601/801 REGISTER 19-1: CONFIGURATION REGISTER 1 HIGH (CONFIG1H: BYTE ADDRESS 0300001h) U-0 -- bit 7 bit 7-2 bit 2-0 Unimplemented: Read as '0' FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = EC oscillator 00 = LP oscillator Legend: r = Reserved R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/P-1 FOSC1 R/P-1 FOSC0 bit 0 REGISTER 19-2: CONFIGURATION REGISTER 2 LOW (CONFIG2L: BYTE ADDRESS 300002h) U-0 -- bit 7 R/P-1 BW U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/P-1 PWRTEN bit 0 bit 7 bit 6 Unimplemented: Read as '0' BW: External Bus Data Width bit 1 = 16-bit external bus mode 0 = 8-bit external bus mode Unimplemented: Read as '0' PWRTEN: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled Legend: r = Reserved R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed bit 5-1 bit 0 DS39541A-page 208 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 REGISTER 19-3: CONFIGURATION REGISTER 2 HIGH (CONFIG2H: BYTE ADDRESS 300003H) U-0 -- bit 7 bit 7-4 bit 3-1 Unimplemented: Read as '0' WDTPS2:WDTPS0: Watchdog Timer Postscale Select bits 000 =1:128 001 =1:64 010 =1:32 011 =1:16 100 =1:8 101 =1:4 110 =1:2 111 =1:1 WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit) Legend: r = Reserved R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed U-0 -- U-0 -- U-0 -- R/P-1 WDTPS2 R/P-1 R/P-1 R/P-1 WDTEN bit 0 WDTPS1 WDTPS0 bit 0 REGISTER 19-4: CONFIGURATION REGISTER 4 LOW (CONFIG4L: BYTE ADDRESS 300006H) R/P-1 r bit 7 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/P-1 -- R/P-1 STVREN bit 0 bit 7 bit 6-1 bit 0 Reserved: Maintain as `1' Unimplemented: Read as '0' STVREN: Stack Full/Underflow RESET Enable bit 1 = Stack Full/Underflow will cause RESET 0 = Stack Full/Underflow will not cause RESET Legend: r = Reserved R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed 2001 Microchip Technology Inc. Advance Information DS39541A-page 209 PIC18C601/801 19.2 Watchdog Timer (WDT) The Watchdog Timer is a free running on-chip RC oscillator, which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKI pin. That means that the WDT will run, even if the clock on the OSC1/CLKI and OSC2/CLKO pins of the device has been stopped; for example, by execution of a SLEEP instruction. During normal operation, a WDT time-out generates a device RESET (Watchdog Timer Reset). If the device is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation (Watchdog Timer Wake-up). The TO bit in the RCON register will be cleared upon a WDT time-out. By default, the Watchdog Timer is disabled by configuration to allow software control over Watchdog Timer operation. If the WDT is enabled by configuration, software execution may not disable this function. When the Watchdog Timer is disabled by configuration, the SWDTEN bit in the WDTCON register enables/ disables the operation of the WDT. The WDT time-out period values may be found in the Electrical Specifications section under parameter #31. Values for the WDT postscaler may be assigned by using configuration bits WDPS<3:1> in CONFIG2H register. If the Watchdog Timer is disabled by configuration, values for the WDT postscaler may be assigned using the SWDPS bits in the WDTCON register. Note 1: The CLRWDT and SLEEP instructions clear the WDT and the postscaler, if assigned to the WDT, and prevent it from timing out and generating a device RESET condition. 2: When a CLRWDT instruction is executed and the prescaler is assigned to the WDT, the prescaler count will be cleared, but the prescaler assignment is not changed. 19.2.1 CONTROL REGISTER Register 19-5 shows the WDTCON register. This is a readable and writable register. It contains control bits to control the Watchdog Timer from user software. If the Watchdog Timer is enabled by configuration, this register setting is ignored. REGISTER 19-5: WDTCON REGISTER U-0 -- bit 7 U-0 -- U-0 -- U-0 -- R/W-0 SWDPS2 R/W-0 R/W-0 R/W-0 bit 0 SWDPS1 SWDPS0 SWDTEN bit 7-4 bit 3-1 Unimplemented: Read as '0' SWDPS2:SWDPS0: Software Watchdog Timer Postscale Select bits 111 = 1:128 110 = 1:64 101 = 1:32 100 = 1:16 011 = 1:8 010 = 1:4 001 = 1:2 000 = 1:1 SWDTEN: Software Controlled Watchdog Timer Enable bit 1 = Watchdog Timer is on 0 = Watchdog Timer is turned off if it is not disabled Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 0 DS39541A-page 210 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 19.2.2 WDT POSTSCALER The WDT has a postscaler that can extend the WDT Reset period. The postscaler may be programmed by the user software or is selected by configuration bits WDTPS<2:0> in the CONFIG2H register. If the device has the Watchdog Timer enabled by configuration bits, the device will use predefined set postscaler value. If the device has the Watchdog Timer disabled by configuration bits, user software can set desired postscaler value. When the device has the Watchdog Timer enabled by configuration bits, by default, Watchdog postscaler of 1:128 is selected. FIGURE 19-1: Watchdog Timer Block Diagram WDT Timer Postscaler 8 SWDTEN bit 8 - to - 1 MUX WDTPS2:WDTPS0 WDT Time-out Note: WDPS2:WDPS0 are bits in a configuration register. TABLE 19-2: Name CONFIG2H RCON WDTCON SUMMARY OF WATCHDOG TIMER REGISTERS Bit 7 -- IPEN -- Bit 6 -- r -- Bit 5 -- -- -- Bit 4 -- RI -- Bit 3 WDTPS2 TO SWDPS2 Bit 2 WDTPS1 PD SWDPS1 Bit 1 WDTPS0 POR SWDPS0 Bit 0 WDTEN r SWDTEN Legend: Shaded cells are not used by the Watchdog Timer. 2001 Microchip Technology Inc. Advance Information DS39541A-page 211 PIC18C601/801 19.3 Power-down Mode (SLEEP) Power-down mode is entered by executing a SLEEP instruction. Upon entering into Power-down mode, the following actions are performed: 1. 2. 3. 4. 5. Watchdog Timer is cleared and kept running. PD bit in RCON register is cleared. TO bit in RCON register is set. Oscillator driver is turned off. I/O ports maintain the status they had before the SLEEP instruction was executed. External MCLR Reset will cause a device RESET. All other events are considered a continuation of program execution and will cause a "wake-up". The TO and PD bits in the RCON register can be used to determine the cause of the device RESET. The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The TO bit is cleared, if a WDT time-out occurred (and caused wake-up). When the SLEEP instruction is being executed, the next instruction (PC + 2) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction and then branches to the interrupt address. In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. To achieve lowest current consumption, follow these steps before switching to Power-down mode: 1. Place all I/O pins at either VDD or VSS and ensure no external circuitry is drawing current from I/O pin. Power-down A/D and external clocks. Pull all hi-impedance inputs to high or low, externally. Place T0CKI at VSS or VDD. Current consumption by PORTB on-chip pullups should be taken into account and disabled, if necessary. 2. 3. 4. 5. 19.3.2 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If an interrupt condition (interrupt flag bit and interrupt enable bits are set) occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT postscaler will not be cleared, the TO bit will not be set and PD bits will not be cleared. * If the interrupt condition occurs during or after the execution of a SLEEP instruction, the device will immediately wake-up from sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT postscaler will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction. The MCLR pin must be at a logic high level (VIHMC). 19.3.1 WAKE-UP FROM SLEEP The device can wake-up from SLEEP through one of the following events: 1. 2. 3. External RESET input on MCLR pin. Watchdog Timer Wake-up (if WDT was enabled). Interrupt from INT pin, RB port change, or a peripheral interrupt. The following peripheral interrupts can wake the device from SLEEP: TMR1 interrupt. Timer1 must be operating as an asynchronous counter. 5. TMR3 interrupt. Timer3 must be operating as an asynchronous counter. 6. CCP Capture mode interrupt. 7. Special event trigger (Timer1 in Asynchronous mode using an external clock). 8. MSSP (START/STOP) bit detect interrupt. 9. MSSP transmit or receive in Slave mode (SPI/I2C). 10. USART RX or TX (Synchronous Slave mode). 11. A/D conversion (when A/D clock source is RC). Other peripherals cannot generate interrupts, since during SLEEP, no on-chip clocks are present. 4. DS39541A-page 212 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 FIGURE 19-2: OSC1 CLKOUT(4) INT pin INTIF bit GIEH bit Processor in SLEEP INSTRUCTION FLOW PC PC PC+2 Inst(PC + 2) SLEEP PC+4 PC+4 Inst(PC + 4) Inst(PC + 2) Dummy cycle PC + 4 0008h Inst(0008h) Dummy cycle 000Ah Inst(000Ah) Inst(0008h) Instruction Inst(PC) = SLEEP Fetched Instruction Inst(PC - 1) Executed Interrupt Latency(3) TOST(2) WAKE-UP FROM SLEEP THROUGH INTERRUPT(1,2) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Note 1: HS or LP oscillator mode assumed. 2: GIE set is assumed. In this case, after wake- up, the processor jumps to the interrupt routine. If GIE is cleared, execution will continue in-line. 3: TOST = 1024TOSC (drawing not to scale). This delay will not occur for RC and EC osc modes. 4: CLKOUT is not available in these oscillator modes, but shown here for timing reference. 2001 Microchip Technology Inc. Advance Information DS39541A-page 213 PIC18C601/801 NOTES: DS39541A-page 214 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 20.0 INSTRUCTION SET SUMMARY The literal instructions may use some of the following operands: * A literal value to be loaded into a file register (represented by 'k') * The desired FSR register to load the literal value into (represented by 'f') * No operand required (specified by '--') The control instructions may use some of the following operands: * A program memory address (represented by 'n') * The mode of the Call or Return instructions (represented by 's') * The mode of the Table Read and Table Write instructions (represented by 'm') * No operand required (specified by '--') All instructions are a single word, except for four double word instructions. These four instructions were made double word instructions so that all the required information is available in these 32 bits. In the second word, the 4 MSbs are 1's. If this second word is executed as an instruction (by itself), it will execute as a NOP. All single word instructions are executed in a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a NOP.The double word instructions execute in two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Two word branch instructions (if true) would take 3 s. Figure 20-1 shows the general formats that the instructions can have. All examples use the format `nnh' to represent a hexadecimal number, where `h' signifies a hexadecimal digit. The Instruction Set Summary, shown in Table 20-2, lists the instructions recognized by the Microchip assembler (MPASMTM). Section 20.1 provides a description of each instruction. The PIC18C601/801 instruction set adds many enhancements to the previous PICmicro(R) instruction sets, while maintaining an easy migration path from them. With few exceptions, instructions are a single program memory word (16-bits). Each single word instruction is divided into an OPCODE, which specifies the instruction type, and one or more operands which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: * * * * Byte-oriented operations Bit-oriented operations Literal operations Control operations The PIC18C601/801 instruction set summary in Table 20-2 lists byte-oriented, bit-oriented, literal and control operations. Table 20-1 shows the opcode field descriptions. Most byte-oriented instructions have three operands: 1. 2. 3. The file register (represented by 'f') The destination of the result (represented by 'd') The accessed memory (represented by 'a') The file register designator `f' specifies which file register is to be used by the instruction. The destination designator `d' specifies where the result of the operation is to be placed. If 'd' is zero, the result is placed in the WREG register. If 'd' is one, the result is placed in the file register specified in the instruction. All bit-oriented instructions have three operands: 1. 2. 3. The file register (represented by 'f') The bit in the file register (represented by 'b') The accessed memory (represented by 'a') The bit field designator 'b' selects the number of the bit affected by the operation, while the file register designator 'f' represents the number of the file in which the bit is located. 2001 Microchip Technology Inc. Advance Information DS39541A-page 215 PIC18C601/801 TABLE 20-1: Field a OPCODE FIELD DESCRIPTIONS Description RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register ACCESS = 0: RAM access bit symbol BANKED = 1: RAM access bit symbol Bit address within an 8-bit file register (0 to 7) Bank Select Register. Used to select the current RAM bank. Destination select bit; d = 0: store result in WREG, d = 1: store result in file register f. Destination either the WREG register or the specified register file location 8-bit Register file address (00h to FFh) 12-bit Register file address (000h to FFFh). This is the source address. 12-bit Register file address (000h to FFFh). This is the destination address. Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value) Label name The mode of the TBLPTR register for the Table Read and Table Write instructions Only used with Table Read and Table Write instructions: No change to register (such as TBLPTR with Table reads and writes) Post-Increment register (such as TBLPTR with Table reads and writes) Post-Decrement register (such as TBLPTR with Table reads and writes) Pre-Increment register (such as TBLPTR with Table reads and writes) The relative address (2's complement number) for relative branch instructions, or the direct address for Call/Branch and Return instructions Product of Multiply high byte (Register at address FF4h) Product of Multiply low byte (Register at address FF3h) Fast Call / Return mode select bit. s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) Unused or Unchanged (Register at address FE8h) W = 0: Destination select bit symbol Working register (accumulator) (Register at address FE8h) Don't care (0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. 21-bit Table Pointer (points to a Program Memory location) (Register at address FF6h) 8-bit Table Latch (Register at address FF5h) Top-of-Stack Program Counter Program Counter Low Byte (Register at address FF9h) Program Counter High Byte Program Counter High Byte Latch (Register at address FFAh) Program Counter Upper Byte Latch (Register at address FFBh) Global Interrupt Enable bit Watchdog Timer Time-out bit Power-down bit ALU status bits Carry, Digit Carry, Zero, Overflow, Negative Optional Contents Assigned to Register bit field In the set of User defined term (font is courier) ACCESS BANKED bbb BSR d dest f fs fd k label mm * *+ *+* n PRODH PRODL s u W WREG x TBLPTR TABLAT TOS PC PCL PCH PCLATH PCLATU GIE WDT TO PD C, DC, Z, OV, N [ ( ] ) <> italics DS39541A-page 216 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 FIGURE 20-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 15 10 OPCODE 9 d 87 a 0 f (FILE #) ADDWF MYREG, W Example Instruction d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select Bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 OPCODE 15 12 11 1111 0 f (Source FILE #) 0 f (Destination FILE #) MOVFF MYREG1, MYREG2 f = 12-bit file register address Bit-oriented file register operations 15 12 11 9 87 OPCODE b (BIT #) a 0 f (FILE #) BSF MYREG, bit b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select Bank f = 8-bit file register address Literal operations 15 OPCODE k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 OPCODE 15 1111 8 7 k (literal) 0 MOVLW 7Fh 87 n<7:0> (literal) 0 GOTO Label 12 11 n<19:8> (literal) 0 n = 20-bit immediate value 15 OPCODE 15 1111 87 S n<7:0> (literal) 0 CALL MYFUNC 0 12 11 n<19:8> (literal) S = Fast bit 15 OPCODE 15 OPCODE 15 11 10 n<10:0> (literal) 87 n<7:0> (literal) 6 OPCODE f 11 1111 0000 0 BRA MYFUNC 0 BC MYFUNC 4 0 k<11:8>(lit.) 0 LFSR FSR0, 100h 15 7 k<7:0> (literal) 2001 Microchip Technology Inc. Advance Information DS39541A-page 217 PIC18C601/801 TABLE 20-2: Mnemonic, Operands PIC18C601/801 INSTRUCTION SET 16-Bit Instruction Word Description Cycles MSb 1 1 1 1 1 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 2 1 1 1 1 1 1 1 1 1 1 1 0010 0010 0001 0110 0001 0110 0110 0110 0000 0010 0100 0010 0011 0100 0001 0101 1100 1111 0110 0000 0110 0011 0100 0011 0100 0110 0101 0101 0101 01da 01da 01da 101a 11da 001a 010a 000a 01da 11da 11da 10da 11da 10da 00da 00da ffff ffff 111a 001a 110a 01da 01da 00da 00da 100a 01da 11da 10da 10da 011a 10da ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff LSb ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS f [,d [,a]] Add WREG and f ADDWF ADDWFC f [,d [,a]] Add WREG and Carry bit to f f [,d [,a]] AND WREG with f ANDWF CLRF f [,a] Clear f f [,d [,a]] Complement f COMF CPFSEQ f [,a] Compare f with WREG, skip = CPFSGT f [,a] Compare f with WREG, skip > CPFSLT f [,a] Compare f with WREG, skip < f [,d [,a]] Decrement f DECF DECFSZ f [,d [,a]] Decrement f, Skip if 0 DCFSNZ f [,d [,a]] Decrement f, Skip if Not 0 INCF f [,d [,a]] Increment f f [,d [,a]] Increment f, Skip if 0 INCFSZ f [,d [,a]] Increment f, Skip if Not 0 INFSNZ f [,d [,a]] Inclusive OR WREG with f IORWF f [,d [,a]] Move f MOVF fs, fd MOVFF Move fs (source) to 1st word fd (destination)2nd word MOVWF f [,a] Move WREG to f MULWF Multiply WREG with f f [,a] NEGF Negate f f [,a] RLCF f [,d [,a]] Rotate Left f through Carry RLNCF f [,d [,a]] Rotate Left f (No Carry) RRCF f [,d [,a]] Rotate Right f through Carry RRNCF f [,d [,a]] Rotate Right f (No Carry) SETF Set f f [,a] SUBFWB f [,d [,a]] Subtract f from WREG with borrow SUBWF f [,d [,a]] Subtract WREG from f SUBWFB f [,d [,a]] Subtract WREG from f with borrow SWAPF f [,d [,a]] Swap nibbles in f TSTFSZ f [,a] Test f, skip if 0 XORWF f [,d [,a]] Exclusive OR WREG with f BIT-ORIENTED FILE REGISTER OPERATIONS C, DC, Z, OV, N C, DC, Z, OV, N Z, N Z Z, N None None None C, DC, Z, OV, N None None C, DC, Z, OV, N None None Z, N Z, N None None None C, DC, Z, OV, N C, Z, N Z, N C, Z, N Z, N None C, DC, Z, OV, N 1, 2, 6 1, 2, 6 1,2, 6 2, 6 1, 2, 6 4, 6 4, 6 1, 2, 6 1, 2, 3, 4, 6 1, 2, 3, 4, 6 1, 2, 6 1, 2, 3, 4, 6 4, 6 1, 2, 6 1, 2, 6 1, 6 6 6 1, 2, 6 6 1, 2, 6 6 6 6 1, 2, 6 ffff C, DC, Z, OV, N 6 ffff C, DC, Z, OV, N 1, 2, 6 ffff None ffff None ffff Z, N 4, 6 1, 2, 6 6 0011 1 1 (2 or 3) 0110 0001 1 BCF f, b [,a] Bit Clear f 1 1001 bbba ffff ffff None 1, 2, 6 BSF f, b [,a] Bit Set f 1 1000 bbba ffff ffff None 1, 2, 6 BTFSC f, b [,a] Bit Test f, Skip if Clear 1 (2 or 3) 1011 bbba ffff ffff None 3, 4, 6 BTFSS f, b [,a] Bit Test f, Skip if Set 1 (2 or 3) 1010 bbba ffff ffff None 3, 4, 6 BTG f [,d [,a]] Bit Toggle f 1 0111 bbba ffff ffff None 1, 2, 6 Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory locations have a valid instruction. 5: If the table write starts the write cycle to internal memory, the write will continue until terminated. 6: Microchip's MPASMTM Assembler automatically defaults destination bit 'd' to '1', while access bit 'a' defaults to '1' or '0', according to address of register being used. DS39541A-page 218 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 TABLE 20-2: Mnemonic, Operands PIC18C601/801 INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Description Cycles MSb 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 1 (2) 1 (2) 2 1 1 2 1 1 1 1 2 1 2 1110 1110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 0010 0110 0011 0111 0101 0001 0100 0nnn 0000 110s kkkk 0000 0000 1111 kkkk 0000 xxxx 0000 0000 1nnn 0000 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1111 0001 LSb nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0100 0111 kkkk kkkk 0000 xxxx 0110 0101 nnnn 1111 000s Status Affected Notes CONTROL OPERATIONS BC n Branch if Carry BN n Branch if Negative BNC n Branch if Not Carry BNN n Branch if Not Negative BNOV n Branch if Not Overflow BNZ n Branch if Not Zero BOV n Branch if Overflow BRA n Branch Unconditionally BZ n Branch if Zero CALL n, s Call subroutine1st word 2nd word CLRWDT -- Clear Watchdog Timer DAW -- Decimal Adjust WREG GOTO n Go to address1st word 2nd word NOP -- No Operation NOP -- No Operation (Note 4) POP -- Pop top of return stack (TOS) PUSH -- Push top of return stack (TOS) RCALL n Relative Call RESET Software device RESET RETFIE s Return from interrupt enable RETLW RETURN SLEEP Note 1: None None None None None None None None None None TO, PD C None 2: 3: 4: 5: 6: None None None None None All GIE/GIEH, PEIE/GIEL k Return with literal in WREG 2 0000 1100 kkkk kkkk None Return from Subroutine s 0000 0000 0001 001s None 2 -- Go into Standby mode 1 0000 0000 0000 0011 TO, PD When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory locations have a valid instruction. If the table write starts the write cycle to internal memory, the write will continue until terminated. Microchip's MPASMTM Assembler automatically defaults destination bit 'd' to '1', while access bit 'a' defaults to '1' or '0', according to address of register being used. 2001 Microchip Technology Inc. Advance Information DS39541A-page 219 PIC18C601/801 TABLE 20-2: Mnemonic, Operands PIC18C601/801 INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes LITERAL OPERATIONS ADDLW k Add literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N ANDLW k AND literal with WREG 1 0000 1011 kkkk kkkk Z, N IORLW k Inclusive OR literal with WREG 1 0000 1001 kkkk kkkk Z, N LFSR f, k Load FSR (f) with a 12-bit 2 1110 1110 00ff kkkk None literal (k) 1111 0000 kkkk kkkk MOVLB k Move literal to BSR<3:0> 1 0000 0001 0000 kkkk None MOVLW k Move literal to WREG 1 0000 1110 kkkk kkkk None MULLW k Multiply literal with WREG 1 0000 1101 kkkk kkkk None RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None SUBLW k Subtract WREG from literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N XORLW k Exclusive OR literal with WREG 1 0000 1010 kkkk kkkk Z, N DATA MEMORY PROGRAM MEMORY OPERATIONS TBLRD* Table Read 2 0000 0000 0000 1000 None TBLRD*+ Table Read with post-increment 0000 0000 0000 1001 None TBLRD*Table Read with post-decrement 0000 0000 0000 1010 None TBLRD+* Table Read with pre-increment 0000 0000 0000 1011 None TBLWT* Table Write 2 (5) 0000 0000 0000 1100 None TBLWT*+ Table Write with post-increment 0000 0000 0000 1101 None TBLWT*Table Write with post-decrement 0000 0000 0000 1110 None TBLWT+* Table Write with pre-increment 0000 0000 0000 1111 None Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory locations have a valid instruction. 5: If the table write starts the write cycle to internal memory, the write will continue until terminated. 6: Microchip's MPASMTM Assembler automatically defaults destination bit 'd' to '1', while access bit 'a' defaults to '1' or '0', according to address of register being used. DS39541A-page 220 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 20.1 ADDLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Instruction Set ADD literal to WREG [ label ] ADDLW 0 k 255 (WREG) + k WREG N,OV, C, DC, Z 0000 1111 kkkk kkkk ADDWF Syntax: Operands: ADD WREG to f [ label ] ADDWF 0 f 255 d [0,1] a [0,1] (WREG) + (f) dest N,OV, C, DC, Z 0010 01da ffff ffff k f [,d [,a]] Operation: Status Affected: Encoding: Description: The contents of WREG are added to the 8-bit literal 'k' and the result is placed in WREG. 1 1 Q2 Read literal 'k' ADDLW Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data 15h Q4 Write to WREG Add WREG to register 'f'. If 'd' is 0, the result is stored in WREG. If 'd' is 1, the result is stored back in register 'f' (default). If 'a' is 0, the Access Bank will be selected. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1 Q2 Read register 'f' ADDWF Words: Cycles: Q Cycle Activity: Q1 Decode Example: WREG N OV C DC Z WREG N OV C DC Z = = = = = = = = = = = = Before Instruction 10h ? ? ? ? ? 25h 0 0 0 0 0 Q3 Process Data REG, W Q4 Write to destination Example: WREG REG N OV C DC Z WREG REG N OV C DC Z = = = = = = = = = = = = = = After Instruction Before Instruction 17h 0C2h ? ? ? ? ? 0D9h 0C2h 1 0 0 0 0 After Instruction 2001 Microchip Technology Inc. Advance Information DS39541A-page 221 PIC18C601/801 ADDWFC Syntax: Operands: ADD WREG and Carry bit to f [ label ] ADDWFC 0 f 255 d [0,1] a [0,1] (WREG) + (f) + (C) dest N,OV, C, DC, Z 0010 00da ffff ffff ANDLW Syntax: Operands: Operation: Status Affected: Encoding: Description: AND literal with WREG [ label ] ANDLW 0 k 255 (WREG) .AND. k WREG N,Z 0000 1011 kkkk kkkk f [,d [,a]] k Operation: Status Affected: Encoding: Description: Add WREG, the Carry Flag and data memory location 'f'. If 'd' is 0, the result is placed in WREG. If 'd' is 1, the result is placed in data memory location 'f'. If 'a' is 0, the Access Bank will be selected. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1 The contents of WREG are AND'ed with the 8-bit literal 'k'. The result is placed in WREG. 1 1 Q2 Read literal 'k' ANDLW Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data 5Fh Q4 Write to WREG Words: Cycles: Q Cycle Activity: Q1 Decode Example: Q2 Read register 'f' ADDWFC Q3 Process Data REG, W Q4 Write to destination Before Instruction WREG N Z WREG N Z = = = = = = 0A3h ? ? 03h 0 0 Example: C REG WREG N OV DC Z = = = = = = = After Instruction Before Instruction 1 02h 4Dh ? ? ? ? After Instruction C REG WREG N OV DC Z = = = = = = = 0 02h 50h 0 0 0 0 DS39541A-page 222 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 ANDWF Syntax: Operands: AND WREG with f [ label ] ANDWF 0 f 255 d [0,1] a [0,1] (WREG) .AND. (f) dest N,Z 0001 01da ffff ffff BC f [,d [,a]] Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Carry [ label ] BC n -128 n 127 if carry bit is '1' (PC) + 2 + 2n PC None 1110 0010 nnnn nnnn Operation: Status Affected: Encoding: Description: The contents of WREG are AND'ed with register 'f'. If 'd' is 0, the result is stored in WREG. If 'd' is 1, the result is stored back in register 'f' (default). If 'a' is 0, the Access Bank will be selected. If 'a' is 1, the bank will be selected as per the BSR value. 1 1 Q2 Read register 'f' ANDWF If the Carry bit is '1', then the program will branch. The 2's complement number '2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2) Words: Cycles: Q Cycle Activity: Q1 Decode Words: Cycles: Q3 Process Data REG, W Q4 Write to destination Q Cycle Activity: If Jump: Q1 Decode No operation Q2 Read literal 'n' No operation Q3 Process Data No operation Q4 Write to PC No operation Example: WREG REG N Z WREG REG N Z = = = = = = = = Before Instruction 17h 0C2h ? ? 02h 0C2h 0 0 If No Jump: Q1 Decode Q2 Read literal 'n' HERE Q3 Process Data BC 5 Q4 No operation After Instruction Example: PC Before Instruction = = = = = address (HERE) 1; address (HERE+12) 0; address (HERE+2) After Instruction If Carry PC If Carry PC 2001 Microchip Technology Inc. Advance Information DS39541A-page 223 PIC18C601/801 BCF Syntax: Operands: Bit Clear f [ label ] BCF 0 f 255 0b7 a [0,1] 0 f None 1001 bbba ffff ffff BN f, b [,a] Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Negative [ label ] BN n -128 n 127 if negative bit is '1' (PC) + 2 + 2n PC None 1110 0110 nnnn nnnn Operation: Status Affected: Encoding: Description: Bit 'b' in register 'f' is cleared. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' = 1, the Bank will be selected as per the BSR value. 1 1 Words: Q2 Read register 'f' BCF Words: Cycles: Q Cycle Activity: Q1 Decode If the Negative bit is '1', then the program will branch. The 2's complement number '2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2) Q3 Process Data FLAG_REG, 7 Q4 Write register 'f' Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation Q2 Read literal 'n' No operation Q3 Process Data No operation Q4 Write to PC No operation Example: Before Instruction FLAG_REG = 0C7h After Instruction FLAG_REG = 47h If No Jump: Q1 Decode Q2 Read literal 'n' HERE Q3 Process Data BN Jump Q4 No operation Example: PC Before Instruction = = = = = address (HERE) 1; address (Jump) 0; address (HERE+2) After Instruction If Negative PC If Negative PC DS39541A-page 224 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 BNC Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Not Carry [ label ] BNC -128 n 127 if carry bit is '0' (PC) + 2 + 2n PC None 1110 0011 nnnn nnnn BNN Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Not Negative [ label ] BNN -128 n 127 if negative bit is '0' (PC) + 2 + 2n PC None 1110 0111 nnnn nnnn n n If the Carry bit is '0', then the program will branch. The 2's complement number '2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2) If the Negative bit is '0', then the program will branch. The 2's complement number '2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2) Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation Q2 Read literal 'n' No operation Q3 Process Data No operation Q4 Write to PC No operation Q2 Read literal 'n' No operation Q3 Process Data No operation Q4 Write to PC No operation If No Jump: Q1 Decode Q2 Read literal 'n' HERE Q3 Process Data BNC Jump Q4 No operation If No Jump: Q1 Decode Q2 Read literal 'n' HERE Q3 Process Data BNN Jump Q4 No operation Example: PC Example: PC Before Instruction = = = = = address (HERE) 0; address (Jump) 1; address (HERE+2) Before Instruction = = = = = address (HERE) 0; address (Jump) 1; address (HERE+2) After Instruction If Carry PC If Carry PC After Instruction If Negative PC If Negative PC 2001 Microchip Technology Inc. Advance Information DS39541A-page 225 PIC18C601/801 BNOV Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Not Overflow [ label ] BNOV -128 n 127 if overflow bit is '0' (PC) + 2 + 2n PC None 1110 0101 nnnn nnnn BNZ Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Not Zero [ label ] BNZ -128 n 127 if zero bit is '0' (PC) + 2 + 2n PC None 1110 0001 nnnn nnnn n n If the Overflow bit is '0', then the program will branch. The 2's complement number '2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2) If the Zero bit is '0', then the program will branch. The 2's complement number '2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2) Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation Q2 Read literal 'n' No operation Q3 Process Data No operation Q4 Write to PC No operation Q2 Read literal 'n' No operation Q3 Process Data No operation Q4 Write to PC No operation If No Jump: Q1 Decode Q2 Read literal 'n' HERE Q3 Process Data BNOV Jump Q4 No operation If No Jump: Q1 Decode Q2 Read literal 'n' HERE Q3 Process Data BNZ Jump Q4 No operation Example: PC Example: PC Before Instruction = = = = = address (HERE) 0; address (Jump) 1; address (HERE+2) Before Instruction = = = = = address (HERE) 0; address (Jump) 1; address (HERE+2) After Instruction If Overflow PC If Overflow PC After Instruction If Zero PC If Zero PC DS39541A-page 226 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 BRA Syntax: Operands: Operation: Status Affected: Encoding: Description: Unconditional Branch [ label ] BRA n -1024 n 1023 (PC) + 2 + 2n PC None 1101 0nnn nnnn nnnn BSF Syntax: Operands: Bit Set f [ label ] BSF 0 f 255 0b7 a [0,1] 1 f None 1000 bbba ffff ffff f, b [,a] Operation: Status Affected: Encoding: Description: Add the 2's complement number '2n' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is a twocycle instruction. 1 2 Q2 Read literal 'n' No operation Words: Cycles: Q Cycle Activity: Q1 Decode No operation Bit 'b' in register 'f' is set. If 'a' is 0 Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value (default). 1 1 Q2 Read register 'f' BSF Words: Cycles: Q3 Process Data No operation Q4 Write to PC No operation Q Cycle Activity: Q1 Decode Q3 Process Data FLAG_REG, 7 Q4 Write register 'f' Example: Example: PC HERE BRA Jump Before Instruction FLAG_REG = = 0Ah 8Ah Before Instruction = = address (HERE) address (Jump) After Instruction FLAG_REG After Instruction PC 2001 Microchip Technology Inc. Advance Information DS39541A-page 227 PIC18C601/801 BTFSC Syntax: Operands: Bit Test File, Skip if Clear [ label ] BTFSC f, b [,a] 0 f 255 0b7 a [0,1] skip if (f) = 0 None 1011 bbba ffff ffff BTFSS Syntax: Operands: Bit Test File, Skip if Set [ label ] BTFSS f, b [,a] 0 f 255 0b<7 a [0,1] skip if (f) = 1 None 1010 bbba ffff ffff Operation: Status Affected: Encoding: Description: Operation: Status Affected: Encoding: Description: If bit 'b' in register 'f' is 0, then the next instruction is skipped. If bit 'b' is 0, then the next instruction fetched during the current instruction execution is discarded, and a NOP is executed instead, making this a twocycle instruction. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2 Read register 'f' Words: Cycles: If bit 'b' in register 'f' is 1 then the next instruction is skipped. If bit 'b' is 1, then the next instruction fetched during the current instruction execution, is discarded and a NOP is executed instead, making this a twocycle instruction. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2 Read register 'f' Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data Q4 No operation Q Cycle Activity: Q1 Decode Q3 Process Data Q4 No operation If skip: Q1 No operation Q2 No operation Q3 No operation Q4 No operation If skip: Q1 No operation Q2 No operation Q3 No operation Q4 No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No operation No operation No operation No operation HERE FALSE TRUE Q4 No operation No operation No operation No operation BTFSC : : If skip and followed by 2-word instruction: Q1 Q2 Q3 No operation No operation No operation No operation HERE FALSE TRUE Q4 No operation No operation No operation No operation BTFSS : : Example: FLAG, 1 Example: FLAG, 1 Before Instruction PC = = = = = address (HERE) 0; address (TRUE) 1; address (FALSE) Before Instruction PC = = = = = address (HERE) 0; address (FALSE) 1; address (TRUE) After Instruction If FLAG<1> PC If FLAG<1> PC After Instruction If FLAG<1> PC If FLAG<1> PC DS39541A-page 228 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 BTG Syntax: Operands: Bit Toggle f [ label ] BTG f, b [,a] 0 f 255 0b<7 a [0,1] (f) f None 0111 bbba ffff ffff BOV Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Overflow [ label ] BOV -128 n 127 if overflow bit is '1' (PC) + 2 + 2n PC None 1110 0100 nnnn nnnn n Operation: Status Affected: Encoding: Description: Bit 'b' in data memory location 'f' is inverted. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1 Words: Q2 Read register 'f' BTG Words: Cycles: Q Cycle Activity: Q1 Decode If the Overflow bit is '1', then the program will branch. The 2's complement number '2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2) Q3 Process Data PORTC, 4 Q4 Write register 'f' Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation Q2 Read literal 'n' No operation Q3 Process Data No operation Q4 Write to PC No operation Example: PORTC PORTC = = Before Instruction: 0111 0101 [75h] 0110 0101 [65h] After Instruction: If No Jump: Q1 Decode Q2 Read literal 'n' HERE Q3 Process Data BOV Jump Q4 No operation Example: PC Before Instruction = = = = = address (HERE) 1; address (Jump) 0; address (HERE+2) After Instruction If Overflow PC If Overflow PC 2001 Microchip Technology Inc. Advance Information DS39541A-page 229 PIC18C601/801 BZ Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Zero [ label ] BZ n -128 n 127 if Zero bit is '1' (PC) + 2 + 2n PC None 1110 0000 nnnn nnnn CALL Syntax: Operands: Operation: Subroutine Call [ label ] CALL k [,s] 0 k 1048575 s [0,1] (PC) + 4 TOS, k PC<20:1>, if s = 1 (WREG) WS, (STATUS) STATUSS, (BSR) BSRS None 1110 1111 110s k19kkk k7kkk kkkk kkkk0 kkkk8 If the Zero bit is '1', then the program will branch. The 2's complement number '2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2) Status Affected: Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) Description: Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation Q2 Read literal 'n' No operation Q3 Process Data No operation Q4 Write to PC No operation Subroutine call of entire 2M byte memory range. First, return address (PC+ 4) is pushed onto the return stack. If 's' = 1, the WREG, STATUS and BSR registers are also pushed into their respective shadow registers, WS, STATUSS and BSRS. If 's' = 0, no update occurs (default). Then the 20-bit value 'k' is loaded into PC<20:1>. CALL is a two-cycle instruction. 2 2 Q2 Read literal 'k'<7:0>, No operation HERE If No Jump: Q1 Decode Words: Q2 Read literal 'n' HERE Q3 Process Data BZ Jump Q4 No operation Cycles: Q Cycle Activity: Q1 Decode Q3 Push PC to stack No operation CALL Q4 Read literal 'k'<19:8>, Write to PC No operation Example: PC Before Instruction = = = = = address (HERE) 1; address (Jump) 0; address (HERE+2) After Instruction If Zero PC If Zero PC No operation Example: PC = THERE, FAST Before Instruction Address (HERE) Address (THERE) Address (HERE + 4) WREGREG BSR STATUS After Instruction PC = TOS = WS = BSRS = STATUSS = DS39541A-page 230 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 CLRF Syntax: Operands: Operation: Status Affected: Encoding: Description: Clear f [label] CLRF 0 f 255 a [0,1] 000h f 1Z Z 0110 101a ffff ffff CLRWDT f [,a] Syntax: Operands: Operation: Clear Watchdog Timer [ label ] CLRWDT None 000h WDT, 000h WDT postscaler, 1 TO, 1 PD TO, PD 0000 0000 0000 0100 Status Affected: Encoding: Description: Clears the contents of the specified register. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1 Q2 Read register 'f' CLRF CLRWDT instruction resets the Watchdog Timer. It also resets the postscaler of the WDT. Status bits TO and PD are set. 1 1 Q2 No operation CLRWDT Words: Cycles: Q Cycle Activity: Q1 Decode Words: Cycles: Q3 Process Data FLAG_REG Q4 Write register 'f' Q Cycle Activity: Q1 Decode Q3 Process Data Q4 No operation Example: Example: Before Instruction FLAG_REG Z = = = = 5Ah ? 00h 0 Before Instruction WDT counter WDT postscaler = = = = = = = = ? ? ? ? 00h 0 1 1 After Instruction FLAG_REG Z TO PD After Instruction WDT counter WDT postscaler TO PD 2001 Microchip Technology Inc. Advance Information DS39541A-page 231 PIC18C601/801 COMF Syntax: Operands: Complement f [ label ] COMF 0 f 255 d [0,1] a [0,1] ( f ) dest N,Z 0001 11da ffff ffff CPFSEQ f [,d [,a]] Syntax: Operands: Operation: Compare f with WREG, skip if f = WREG [ label ] CPFSEQ 0 f 255 a [0,1] (f) - (WREG), skip if (f) = (WREG) (unsigned comparison) None 0110 001a ffff ffff f [,a] Operation: Status Affected: Encoding: Description: Status Affected: Encoding: Description: The contents of register 'f' are complemented. If 'd' is 0 the result is stored in WREG. If 'd' is 1 the result is stored back in register 'f' (default). If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1 Q2 Read register 'f' Words: Cycles: Q Cycle Activity: Q1 Decode Compares the contents of data memory location 'f' to the contents of WREG by performing an unsigned subtraction. If 'f' = WREG, then the fetched instruction is discarded and a NOP is executed instead making this a two-cycle instruction. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2 Read register 'f' Q3 Process Data Q4 Write to destination Words: Cycles: Example: REG N Z REG WREG N Z = = = = = = = COMF REG Q Cycle Activity: Q1 Decode Q3 Process Data Q4 No operation Before Instruction 13h ? ? 13h 0ECh 1 0 If skip: Q1 No operation Q2 No operation Q3 No operation Q4 No operation After Instruction If skip and followed by 2-word instruction: Q1 Q2 Q3 No operation No operation No operation No operation HERE NEQUAL EQUAL Q4 No operation No operation No operation No operation CPFSEQ REG : : Example: Before Instruction PC Address = WREG = REG = After Instruction If REG = PC = If REG PC = HERE ? ? WREG; Address (EQUAL) WREG; Address (NEQUAL) DS39541A-page 232 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 CPFSGT Syntax: Operands: Operation: Compare f with WREG, skip if f > WREG [ label ] CPFSGT 0 f 255 a [0,1] (f) - (WREG), skip if (f) > (WREG) (unsigned comparison) None 0110 010a ffff ffff CPFSLT Syntax: Operands: Operation: Compare f with WREG, skip if f < WREG [ label ] CPFSLT 0 f 255 a [0,1] (f) - (WREG), skip if (f) < (WREG) (unsigned comparison) None 0110 000a ffff ffff f [,a] f [,a] Status Affected: Encoding: Description: Status Affected: Encoding: Description: Compares the contents of data memory location 'f' to the contents of the WREG by performing an unsigned subtraction. If the contents of 'f' are greater than the contents of , then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2 Read register 'f' Compares the contents of data memory location 'f' to the contents of WREG by performing an unsigned subtraction. If the contents of 'f' are less than the contents of WREG, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If 'a' is 0, the Access Bank will be selected. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2 Read register 'f' Words: Cycles: Words: Cycles: Q Cycle Activity: Q1 Decode Q Cycle Activity: Q1 Decode Q3 Process Data Q4 No operation Q3 Process Data Q4 No operation If skip: Q1 Q2 No operation If skip: Q1 No operation Q3 No operation Q4 No operation Q2 No operation Q3 No operation Q4 No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No operation No operation No operation No operation HERE NGREATER GREATER If skip and followed by 2-word instruction: Q1 Q2 Q3 No operation No operation No operation No operation HERE NLESS LESS Q4 No operation No operation Q4 No operation No operation No operation No operation CPFSGT REG : : No operation No operation CPFSLT REG : : Example: Example: Before Instruction PC WREG = = < = = Address (HERE) ? WREG; Address (LESS) WREG; Address (NLESS) Before Instruction PC = WREG = After Instruction If REG > PC = If REG PC = Address (HERE) ? WREG; Address (GREATER) WREG; Address (NGREATER) After Instruction If REG PC If REG PC 2001 Microchip Technology Inc. Advance Information DS39541A-page 233 PIC18C601/801 DAW Syntax: Operands: Operation: Decimal Adjust WREG Register [label] DAW None If [WREG<3:0> >9] or [DC = 1] then (WREG<3:0>) + 6 W<3:0>; else (WREG<3:0>) W<3:0>; If [WREG<7:4> >9] or [C = 1] then (WREG<7:4>) + 6 WREG<7:4>; else (WREG<7:4>) WREG<7:4>; Status Affected: Encoding: Description: C 0000 0000 0000 0111 DECF Syntax: Operands: Decrement f [ label ] DECF f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f) - 1 dest C,DC,N,OV,Z 0000 01da ffff ffff Operation: Status Affected: Encoding: Description: Decrement register 'f'. If 'd' is 0, the result is stored in WREG. If 'd' is 1, the result is stored back in register 'f' (default). If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1 Q2 Read register 'f' DECF DAW adjusts the eight-bit value in WREG resulting from the earlier addition of two variables (each in packed BCD format) and produces a correct packed BCD result. 1 1 Q2 Q3 Process Data Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data CNT Q4 Write to destination Words: Cycles: Q Cycle Activity: Q1 Decode Q4 Write WREG Example: CNT Z CNT Z = = = = Read register WREG DAW Before Instruction 01h 0 00h 1 Example1: WREG C DC WREG C DC = = = = = = Before Instruction 0A5h 0 0 05h 1 0 After Instruction After Instruction Example 2: Before Instruction WREG C DC WREG C DC = = = = = = 0CEh 0 0 34h 1 0 After Instruction DS39541A-page 234 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 DECFSZ Syntax: Operands: Decrement f, skip if 0 [ label ] DECFSZ f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f) - 1 dest, skip if result = 0 None 0010 11da ffff ffff DCFSNZ Syntax: Operands: Decrement f, skip if not 0 [label] DCFSNZ f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f) - 1 dest, skip if result 0 None 0100 11da ffff ffff Operation: Status Affected: Encoding: Description: Operation: Status Affected: Encoding: Description: The contents of register 'f' are decremented. If 'd' is 0, the result is placed in WREG. If 'd' is 1, the result is placed back in register 'f' (default). If the result is 0, the next instruction, which is already fetched, is discarded, and a NOP is executed instead, making it a two-cycle instruction. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2 Read register 'f' The contents of register 'f' are decremented. If 'd' is 0, the result is placed in WREG. If 'd' is 1, the result is placed back in register 'f' (default). If the result is not 0, the next instruction, which is already fetched, is discarded, and a NOP is executed instead, making it a two-cycle instruction. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2 Read register 'f' Words: Cycles: Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data Q4 Write to destination Q Cycle Activity: Q1 Decode Q3 Process Data Q4 Write to destination If skip: Q1 No operation If skip: Q2 No operation Q3 No operation Q4 No operation Q1 No operation Q2 No operation Q3 No operation Q4 No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No operation No operation No operation No operation HERE CONTINUE Q4 No operation No operation CNT LOOP If skip and followed by 2-word instruction: Q1 Q2 Q3 No operation No operation No operation No operation HERE ZERO NZERO Q4 No operation No operation No operation No operation DECFSZ GOTO No operation No operation DCFSNZ : : TEMP Example: Example: Before Instruction PC CNT If CNT PC If CNT PC = = = = = Address (HERE) CNT - 1 0; Address (CONTINUE) 0; Address (HERE+2) Before Instruction TEMP = = = = = ? TEMP - 1, 0; Address (ZERO) 0; Address (NZERO) After Instruction After Instruction TEMP If TEMP PC If TEMP PC 2001 Microchip Technology Inc. Advance Information DS39541A-page 235 PIC18C601/801 GOTO Syntax: Operands: Operation: Status Affected: Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) Description: Unconditional Branch [ label ] GOTO k 0 k 1048575 k PC<20:1> None 1110 1111 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 INCF Syntax: Operands: Increment f [ label ] INCF f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f) + 1 dest C,DC,N,OV,Z 0010 10da ffff ffff Operation: Status Affected: Encoding: Description: GOTO allows an unconditional branch anywhere within entire 2M byte memory range. The 20-bit value 'k' is loaded into PC<20:1>. GOTO is always a two-cycle instruction. 2 2 Q2 Read literal 'k'<7:0>, No operation Words: Cycles: Q Cycle Activity: Q1 Decode The contents of register 'f' are incremented. If 'd' is 0, the result is placed in WREG. If 'd' is 1, the result is placed back in register 'f' (default). If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1 Q2 Read register 'f' INCF Words: Q3 No operation No operation Q4 Read literal 'k'<19:8>, Write to PC No operation Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data CNT Q4 Write to destination No operation Example: Example: PC = GOTO THERE Before Instruction CNT Z C DC CNT Z C DC = = = = = = = = 0FFh 0 ? ? 00h 1 1 1 After Instruction Address (THERE) After Instruction DS39541A-page 236 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 INCFSZ Syntax: Operands: Increment f, skip if 0 [ label ] INCFSZ f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f) + 1 dest, skip if result = 0 None 0011 11da ffff ffff INFSNZ Syntax: Operands: Increment f, skip if not 0 [label] INFSNZ f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f) + 1 dest, skip if result 0 None 0100 10da ffff ffff Operation: Status Affected: Encoding: Description: Operation: Status Affected: Encoding: Description: The contents of register 'f' are incremented. If 'd' is 0, the result is placed in WREG. If 'd' is 1, the result is placed back in register 'f' (default). If the result is 0, the next instruction, which is already fetched, is discarded, and a NOP is executed instead, making it a two-cycle instruction. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2 Read register 'f' The contents of register 'f' are incremented. If 'd' is 0, the result is placed in WREG. If 'd' is 1, the result is placed back in register 'f' (default). If the result is not 0, the next instruction, which is already fetched, is discarded, and a NOP is executed instead, making it a two-cycle instruction. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2 Read register 'f' Words: Cycles: Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data Q4 Write to destination Q Cycle Activity: Q1 Decode Q3 Process Data Q4 Write to destination If skip: Q1 No operation If skip: Q2 No operation Q3 No operation Q4 No operation Q1 No operation Q2 No operation Q3 No operation Q4 No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No operation No operation No operation No operation HERE NZERO ZERO Q4 No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No operation No operation No operation No operation HERE ZERO NZERO Q4 No operation No operation No operation No operation INCFSZ : : CNT No operation No operation INFSNZ REG Example: Example: Before Instruction PC CNT If CNT PC If CNT PC = = = = = Address (HERE) CNT + 1 0; Address (ZERO) 0; Address (NZERO) Before Instruction PC REG If REG PC If REG PC = = Address (HERE) REG + 1 0; Address (NZERO) 0; Address (ZERO) After Instruction After Instruction = = = 2001 Microchip Technology Inc. Advance Information DS39541A-page 237 PIC18C601/801 IORLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Inclusive OR literal with WREG [ label ] IORLW k 0 k 255 (WREG) .OR. k WREG N,Z 0000 1001 kkkk kkkk IORWF Syntax: Operands: Inclusive OR WREG with f [ label ] IORWF f [,d [,a]] 0 f 255 d [0,1] a [0,1] (WREG) .OR. (f) dest N,Z 0001 00da ffff ffff Operation: Status Affected: Encoding: Description: The contents of WREG are OR'ed with the eight bit literal 'k'. The result is placed in WREG. 1 1 Q2 Read literal 'k' IORLW Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data 35h Q4 Write to WREG Inclusive OR WREG with register 'f'. If 'd' is 0, the result is placed in WREG. If 'd' is 1, the result is placed back in register 'f' (default). If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1 Q2 Read register 'f' IORWF Words: Example: WREG N Z WREG N Z = = = = = = Cycles: Q Cycle Activity: Q1 Decode Before Instruction 9Ah ? ? 0BFh 1 0 Q3 Process Data RESULT, W Q4 Write to destination After Instruction Example: RESULT WREG N Z RESULT WREG N Z = = = = = = = = Before Instruction 13h 91h ? ? 13h 93h 1 0 After Instruction DS39541A-page 238 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 LFSR Syntax: Operands: Operation: Status Affected: Encoding: Description: Load FSR [ label ] LFSR f,k 0f2 0 k 4095 k FSRf None 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk MOVF Syntax: Operands: Move f [ label ] MOVF f [,d [,a]] 0 f 255 d [0,1] a [0,1] f dest N,Z 0101 00da ffff ffff Operation: Status Affected: Encoding: Description: The 12-bit literal 'k' is loaded into the file select register pointed to by 'f'. 2 2 Q2 Read literal 'k' MSB Read literal 'k' LSB Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data Process Data Q4 Write literal 'k' MSB to FSRfH Write literal 'k' to FSRfL The contents of register 'f' is moved to a destination dependent upon the status of 'd'. If 'd' is 0, the result is placed in WREG. If 'd' is 1, the result is placed back in register 'f' (default). Location 'f' can be anywhere in the 256 byte Bank. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1 Q2 Read register 'f' MOVF Words: Cycles: Q Cycle Activity: Q1 Decode Decode Example: FSR2H FSR2L LFSR FSR2, 3ABh Q3 Process Data REG, W Q4 Write WREG After Instruction = = 03h 0ABh Example: REG WREG N Z Before Instruction = = = = = = = = 22h 0FFh ? ? 22h 22h 0 0 After Instruction REG WREG N Z 2001 Microchip Technology Inc. Advance Information DS39541A-page 239 PIC18C601/801 MOVFF Syntax: Operands: Operation: Status Affected: Encoding: 1st word (source) 2nd word (destin.) Description: Move f to f [label] MOVFF fs,fd 0 fs 4095 0 fd 4095 (fs) fd None 1100 1111 ffff ffff ffff ffff ffffs ffffd MOVLB Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode Move literal to low nibble in BSR [ label ] k BSR None 0000 0001 kkkk kkkk MOVLB k 0 k 255 The 8-bit literal 'k' is loaded into the Bank Select Register (BSR). 1 1 Q2 Read literal 'k' The contents of source register 'fs' are moved to destination register 'fd'. Location of source 'fs' can be anywhere in the 4096 byte data space (000h to FFFh), and location of destination 'fd' can also be anywhere from 000h to FFFh. Either source or destination can be WREG (a useful special situation). MOVFF is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an I/O port). The MOVFF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. 2 2 (3) Q2 Read register 'f' (src) No operation No dummy read Q3 Process Data Q4 Write literal 'k' to BSR Example: MOVLB 05h Before Instruction BSR register = = 02h 05h After Instruction BSR register Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data No operation Q4 No operation Write register 'f' (dest) Decode Example: REG1 REG2 MOVFF REG1, REG2 Before Instruction = = = = 33h 11h 33h, 33h After Instruction REG1 REG2 DS39541A-page 240 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 MOVLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode Move literal to WREG [ label ] MOVLW k 0 k 255 k WREG None 0000 1110 kkkk kkkk MOVWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Move WREG to f [ label ] MOVWF f [,a] 0 f 255 a [0,1] (WREG) f None 0110 111a ffff ffff The eight bit literal 'k' is loaded into WREG. 1 1 Q2 Read literal 'k' MOVLW Q3 Process Data 5Ah Q4 Write to WREG Move data from WREG to register 'f'. Location 'f' can be anywhere in the 256 byte Bank. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1 Q2 Read register 'f' MOVWF Words: Cycles: Q Cycle Activity: Q1 Decode Example: WREG = After Instruction 0x5A Q3 Process Data REG Q4 Write register 'f' Example: WREG REG WREG REG = = = = Before Instruction 4Fh 0FFh 4Fh 4Fh After Instruction 2001 Microchip Technology Inc. Advance Information DS39541A-page 241 PIC18C601/801 MULLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Multiply Literal with WREG [ label ] MULLW k 0 k 255 (WREG) x k PRODH:PRODL None 0000 1101 kkkk kkkk MULWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Multiply WREG with f [ label ] MULWF f [,a] 0 f 255 a [0,1] (WREG) x (f) PRODH:PRODL None 0000 001a ffff ffff An unsigned multiplication is carried out between the contents of WREG and the 8-bit literal 'k'. The 16-bit result is placed in PRODH:PRODL register pair. PRODH contains the high byte. WREG is unchanged. None of the status flags are affected. Note that neither overflow nor carry is possible in this operation. A zero result is possible but not detected. 1 1 Q2 Read literal 'k' Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data Q4 Write registers PRODH: PRODL An unsigned multiplication is carried out between the contents of WREG and the register file location 'f'. The 16-bit result is stored in the PRODH:PRODL register pair. PRODH contains the high byte. Both WREG and 'f' are unchanged. None of the status flags are affected. Note that neither overflow nor carry is possible in this operation. A zero result is possible but not detected. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1 Q2 Read register 'f' Words: Cycles: Q Cycle Activity: Q1 Decode Example: WREG PRODH PRODL MULLW C4h Before Instruction = = = = = = 0E2h ? ? 0E2h 0ADh 08h Q3 Process Data Q4 Write registers PRODH: PRODL After Instruction WREG PRODH PRODL Example: WREG REG PRODH PRODL MULWF REG Before Instruction = = = = = = = = 0C4h 0B5h ? ? 0C4h 0B5h 8Ah 94h After Instruction WREG REG PRODH PRODL DS39541A-page 242 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 NEGF Syntax: Operands: Operation: Status Affected: Encoding: Description: Negate f [label] NEGF f [,a] 0 f 255 a [0,1] (f)+1f N,OV, C, DC, Z 0110 110a ffff ffff NOP Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode No Operation [ label ] None No operation None 0000 1111 0000 xxxx 0000 xxxx 0000 xxxx NOP Location 'f' is negated using two's complement. The result is placed in the data memory location 'f'. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1 Q2 Read register 'f' NEGF No operation. 1 1 Q2 No operation Q3 No operation Q4 No operation Words: Cycles: Q Cycle Activity: Q1 Decode Example: Q3 Process Data REG Q4 Write register 'f' None. Example: REG N OV C DC Z REG N OV C DC Z = = = = = = = = = = = = Before Instruction 0011 1010 [3Ah] ? ? ? ? ? 1100 0110 [0C6h] 1 0 0 0 0 After Instruction 2001 Microchip Technology Inc. Advance Information DS39541A-page 243 PIC18C601/801 POP Syntax: Operands: Operation: Status Affected: Encoding: Description: Pop Top of Return Stack [ label ] None (TOS) bit bucket None 0000 0000 0000 0110 PUSH Syntax: Operands: Operation: Status Affected: Encoding: Description: Push Top of Return Stack [ label ] None (PC+2) TOS None 0000 0000 0000 0101 POP PUSH The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack. This instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. 1 1 Q2 No operation POP GOTO The PC+2 is pushed onto the top of the return stack. The previous TOS value is pushed down on the stack. This instruction allows implementing a software stack by modifying TOS, and then push it onto the return stack. 1 1 Q2 Push PC+2 onto return stack PUSH Words: Cycles: Q Cycle Activity: Q1 Decode Words: Cycles: Q Cycle Activity: Q1 Decode Q3 No operation Q4 No operation Q3 Pop TOS value Q4 No operation Example: Example: NEW Before Instruction TOS PC 0031A2h 014332h = = 00345Ah 000124h Before Instruction TOS Stack (1 level down) = = After Instruction PC TOS Stack (1 level down) = = = 000126h 000126h 00345Ah After Instruction TOS PC = = 014332h NEW DS39541A-page 244 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 RCALL Syntax: Operands: Operation: Status Affected: Encoding: Description: Relative Call [ label ] RCALL -1024 n 1023 (PC) + 2 TOS, (PC) + 2 + 2n PC None 1101 1nnn nnnn nnnn RESET n Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode Reset [ label ] None Reset all registers and flags that are affected by a MCLR Reset. All 0000 0000 1111 1111 RESET Subroutine call with a jump up to 1K from the current location. First, return address (PC+2) is pushed onto the stack. Then, add the 2's complement number '2n' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is a two-cycle instruction. 1 2 Q2 Read literal 'n' Push PC to stack This instruction provides a way to execute a MCLR Reset in software. 1 1 Q2 Start reset RESET Q3 No operation Q4 No operation Words: Cycles: Q Cycle Activity: Q1 Decode Example: Q3 Process Data After Instruction Q4 Write to PC Registers = Flags* = Reset Value Reset Value No operation No operation HERE No operation RCALL Jump No operation Example: PC = PC = TOS = Before Instruction Address (HERE) Address (Jump) Address (HERE+2) After Instruction 2001 Microchip Technology Inc. Advance Information DS39541A-page 245 PIC18C601/801 RETFIE Syntax: Operands: Operation: Return from Interrupt [ label ] s [0,1] (TOS) PC, 1 GIE/GIEH or PEIE/GIEL, if s = 1 (WS) WREG, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged. None 0000 0000 0001 000s RETLW Syntax: Operands: Operation: Return Literal to WREG [ label ] RETLW k 0 k 255 k W, (TOS) PC, PCLATU, PCLATH are unchanged None 0000 1100 kkkk kkkk RETFIE [s] Status Affected: Encoding: Description: Status Affected: Encoding: Description: Return from Interrupt. Stack is popped and Top-of-Stack (TOS) is loaded into the PC. Interrupts are enabled by setting the either the high or low priority global interrupt enable bit. If 's' = 1, the contents of the shadow registers WS, STATUSS and BSRS are loaded into their corresponding registers, WREG, STATUS and BSR. If 's' = 0, no update of these registers occurs (default). 1 2 W is loaded with the eight-bit literal 'k'. The program counter is loaded from the top of the stack (the return address). The high address latch (PCLATH) remains unchanged. 1 2 Q2 Read literal 'k' No operation Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data No operation Q4 Pop PC from stack, write to WREG No operation No operation Words: Cycles: Q Cycle Activity: Q1 Decode Example: CALL TABLE ; WREG contains table ; offset value ; WREG now has ; table value Q2 No operation Q3 No operation Q4 Pop PC from stack Set GIEH or GIEL : TABLE ADDWF RETLW RETLW : : RETLW No operation No operation RETFIE 1 No operation No operation PCL k0 k1 ; WREG = offset ; Begin table ; Example: After Interrupt kn ; End of table PC WREG BSR STATUS GIE/GIEH, PEIE/GIEL = = = = = TOS WS BSRS STATUSS 1 Before Instruction WREG WREG = = 07h value of kn After Instruction DS39541A-page 246 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 RETURN Syntax: Operands: Operation: Return from Subroutine [ label ] s [0,1] (TOS) PC, if s = 1 (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged None 0000 0000 0001 001s RLCF Syntax: Operands: Rotate Left f through Carry [ label ] RLCF 0 f 255 d [0,1] a [0,1] (f 0011 01da ffff ffff RETURN [s] f [,d [,a]] Operation: Status Affected: Encoding: Description: Status Affected: Encoding: Description: Return from subroutine. The stack is popped and the top of the stack (TOS) is loaded into the program counter. If 's' = 1, the contents of the shadow registers WS, STATUSS and BSRS are loaded into their corresponding registers, WREG, STATUS and BSR. If 's' = 0, no update of these registers occurs (default). 1 2 Q2 No operation No operation The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0 the result is placed in WREG. If 'd' is 1 the result is stored back in register 'f' (default). If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. C register f Words: Cycles: Q Cycle Activity: Q1 Decode No operation Words: Cycles: Q3 Process Data No operation 1 1 Q2 Read register 'f' RLCF Q4 Pop PC from stack No operation Q Cycle Activity: Q1 Decode Q3 Process Data REG, W Q4 Write to destination Example: REG C N Z REG WREG C N Z = = = = = = = = = Before Instruction Example: After Call PC = TOS RETURN FAST RETURN 1110 0110 0 ? ? 1110 0110 1100 1100 1 1 0 After Instruction Before Instruction WRG = STATUS = BSR = 04h 00h 00h 04h 00h 00h TOS After Instruction WREG STATUS BSR PC = = = = 2001 Microchip Technology Inc. Advance Information DS39541A-page 247 PIC18C601/801 RLNCF Syntax: Operands: Rotate Left f (no carry) [ label ] RLNCF 0 f 255 d [0,1] a [0,1] (f 0100 01da ffff ffff RRCF Syntax: Operands: Rotate Right f through Carry [ label ] RRCF f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f 0011 00da ffff ffff f [,d [,a]] Operation: Status Affected: Encoding: Description: Operation: Status Affected: Encoding: Description: The contents of register 'f' are rotated one bit to the left. If 'd' is 0 the result is placed in WREG. If 'd' is 1, the result is stored back in register 'f' (default). If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. register f The contents of register 'f' are rotated one bit to the right through the Carry Flag. If 'd' is 0, the result is placed in WREG. If 'd' is 1, the result is placed back in register 'f' (default). If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. C register f Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Words: Q2 Read register 'f' RLNCF 1 1 Q2 Read register 'f' RRCF Q3 Process Data REG Q4 Write to destination Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data REG, W Q4 Write to destination Example: REG N Z = = = Before Instruction 1010 1011 ? ? Example: REG C N Z REG WREG C N Z = = = = = = = = = Before Instruction 1110 0110 0 ? ? 1110 0110 0111 0011 0 0 0 After Instruction REG N Z = = = 0101 0111 0 0 After Instruction DS39541A-page 248 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 RRNCF Syntax: Operands: Rotate Right f (no carry) [ label ] RRNCF f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f 0100 00da ffff ffff SETF Syntax: Operands: Operation: Status Affected: Encoding: Description: Set f [label] SETF 0 f 255 a [0,1] FFh f None 0110 100a ffff ffff f [,a] Operation: Status Affected: Encoding: Description: The contents of register 'f' are rotated one bit to the right. If 'd' is 0, the result is placed in WREG. If 'd' is 1, the result is placed back in register 'f' (default). If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. register f The contents of the specified register are set to FFh. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1 Q2 Read register 'f' SETF Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data REG Q4 Write register 'f' Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Q2 Read register 'f' RRNCF Example: Q3 Process Data REG Before Instruction Q4 Write to destination REG = = 5Ah 0FFh After Instruction REG Example 1: REG N Z REG N Z = = = = = = Before Instruction 1101 0111 ? ? 1110 1011 1 0 RRNCF REG, 0, 0 After Instruction Example 2: WREG REG N Z WREG REG N Z = = = = = = = = Before Instruction ? 1101 0111 ? ? 1110 1011 1101 0111 1 0 After Instruction 2001 Microchip Technology Inc. Advance Information DS39541A-page 249 PIC18C601/801 SLEEP Syntax: Operands: Operation: Enter SLEEP mode [ label ] SLEEP None 00h WDT, 0 WDT postscaler, 1 TO, 0 PD TO, PD 0000 0000 0000 0011 SUBFWB Syntax: Operands: Subtract f from WREG with borrow [ label ] SUBFWB f [,d [,a]] 0 f 255 d [0,1] a [0,1] (WREG) - (f) - (C) dest N,OV, C, DC, Z 0101 01da ffff ffff Operation: Status Affected: Encoding: Description: Status Affected: Encoding: Description: The power-down status bit (PD) is cleared. The time-out status bit (TO) is set. Watchdog Timer and its postscaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. 1 1 Q2 No operation SLEEP Words: Cycles: Q Cycle Activity: Q1 Decode Subtract register 'f' and carry flag (borrow) from WREG (2's complement method). If 'd' is 0, the result is stored in WREG. If 'd' is 1, the result is stored in register 'f' (default) . If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1 Q2 Read register 'f' Words: Cycles: Q3 Process Data Q4 Go to sleep Q Cycle Activity: Q1 Decode Q3 Process Data Q4 Write to destination Example: TO = PD = TO = PD = ? ? Before Instruction After Instruction 1 0 If WDT causes wake-up, this bit is cleared. DS39541A-page 250 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 SUBFWB (Cont.) Example 1: REG WREG C REG WREG C Z N = = = = = = = = SUBLW SUBFWB REG Subtract WREG from literal [ label ] SUBLW k 0 k 255 k - (WREG) WREG N,OV, C, DC, Z 0000 1000 kkkk kkkk Syntax: Operands: Operation: Status Affected: Encoding: Description: Before Instruction 3 2 1 0FFh 2 0 0 1 ; result is negative SUBFWB REG After Instruction WREG is subtracted from the eight bit literal 'k'. The result is placed in WREG. 1 1 Q2 Read literal 'k' SUBLW Words: Cycles: Q Cycle Activity: Q1 Decode Example 2: REG WREG C REG WREG C Z N = = = = = = = = Before Instruction 2 5 1 2 3 1 0 0 Q3 Process Data 02h Q4 Write to WREG After Instruction Example 1: WREG C ; result is positive REG Before Instruction = = = = = = 1 ? 1 1 0 0 SUBLW After Instruction WREG C Z N ; result is positive Example 3: REG WREG C REG WREG C Z N = = = = = = = = SUBFWB Before Instruction 1 2 0 0 2 1 1 0 After Instruction Example 2: WREG C ; result is zero WREG C Z N = = = = = = 02h Before Instruction 2 ? 0 1 1 0 SUBLW After Instruction ; result is zero Example 3: WREG C WREG C Z N = = = = = = 02h Before Instruction 3 ? 0FFh ; (2's complement) 0 ; result is negative 0 1 After Instruction 2001 Microchip Technology Inc. Advance Information DS39541A-page 251 PIC18C601/801 SUBWF Syntax: Operands: Subtract WREG from f [ label ] SUBWF f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f) - (WREG) dest N,OV, C, DC, Z 0101 11da ffff ffff SUBWF (Cont.) Example 1: REG WREG C REG WREG C Z N = = = = = = = = SUBWF REG Before Instruction 3 2 ? 1 2 1 0 0 SUBWF Operation: Status Affected: Encoding: Description: After Instruction Subtract WREG from register 'f' (2's complement method). If 'd' is 0, the result is stored in WREG. If 'd' is 1, the result is stored back in register 'f' (default). If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1 Q2 Read register 'f' ; result is positive Example 2: REG WREG C REG WREG C Z N = = = = = = = = REG, W Before Instruction 2 2 ? 2 0 1 1 0 SUBWF After Instruction Words: Cycles: Q Cycle Activity: Q1 Decode ; result is zero Q3 Process Data Q4 Write to destination Example 3: REG WREG C REG WREG C Z N = = = = = = = = REG Before Instruction 1 2 ? 0FFh ;(2's complement) 2 0 ; result is negative 0 1 After Instruction DS39541A-page 252 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 SUBWFB Syntax: Operands: Subtract WREG from f with Borrow [ label ] SUBWFB f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f) - (WREG) - (C) dest N,OV, C, DC, Z 0101 10da ffff ffff SUBWFB (Cont.) Example 1: REG WREG C REG WREG C Z N = = = = = = = = SUBWFB REG Before Instruction 19h 0Dh 1 0Ch 0Dh 1 0 0 SUBWFB (0001 1001) (0000 1101) Operation: Status Affected: Encoding: Description: After Instruction (0000 1011) (0000 1101) Subtract WREG and the carry flag (borrow) from register 'f' (2's complement method). If 'd' is 0, the result is stored in WREG. If 'd' is 1, the result is stored back in register 'f' (default). If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1 Q2 Read register 'f' ; result is positive REG, W Example 2: Before Instruction REG WREG C REG WREG C Z N = = = = = = = = 1Bh 1Ah 0 1Bh 00h 1 1 0 SUBWFB (0001 1011) (0001 1010) After Instruction (0001 1011) Words: Cycles: Q Cycle Activity: Q1 Decode ; result is zero Q3 Process Data Q4 Write to destination Example 3: Before Instruction REG WREG C REG WREG C Z N = = = = = = = = REG 03h 0Eh 1 0F5h 0Eh 0 0 1 (0000 0011) (0000 1101) After Instruction (1111 0100) [2's comp] (0000 1101) ; result is negative 2001 Microchip Technology Inc. Advance Information DS39541A-page 253 PIC18C601/801 SWAPF Syntax: Operands: Swap nibbles in f [ label ] SWAPF f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> None 0011 10da ffff ffff Operation: Status Affected: Encoding: Description: The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0, the result is placed in WREG. If 'd' is 1, the result is placed in register 'f' (default). If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1 Q2 Read register 'f' SWAPF Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data REG Q4 Write to destination Example: REG REG = = Before Instruction 53h 35h After Instruction DS39541A-page 254 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 TBLRD Syntax: Operands: Operation: Table Read [ label ] None if TBLRD *, (Prog Mem (TBLPTR)) TABLAT; TBLPTR - No Change; if TBLRD *+, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) +1 TBLPTR; if TBLRD *-, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) -1 TBLPTR; if TBLRD +*, (TBLPTR) +1 TBLPTR; (Prog Mem (TBLPTR)) TABLAT; None 0000 0000 0000 10nn nn=0 * =1 *+ =2 *=3 +* TBLRD (Cont.) Example 1: TBLRD *+ ; TBLRD ( *; *+; *-; +*) Before Instruction TABLAT TBLPTR MEMORY(00A356h) = = = = = TBLRD +* ; 55h 00A356h 34h 34h 00A357h After Instruction TABLAT TBLPTR Example 2: Before Instruction TABLAT TBLPTR MEMORY(01A357h) MEMORY(01A358h) = = = = = = 0AAh 01A357h 12h 34h 34h 01A358h Status Affected: Encoding: After Instruction TABLAT TBLPTR Description: This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2 Mbyte address range. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: * no change * post-increment * post-decrement * pre-increment Words: Cycles: Q Cycle Activity: Q1 Decode No operation 1 2 Q2 No operation No operation (Read Program Memory) Q3 No operation No operation Q4 No operation No operation (Write TABLAT) 2001 Microchip Technology Inc. Advance Information DS39541A-page 255 PIC18C601/801 TBLWT Syntax: Operands: Operation: Table Write [ label ] None if TBLWT*, (TABLAT) Prog Mem (TBLPTR) or Holding Register; TBLPTR - No Change; if TBLWT*+, (TABLAT) Prog Mem (TBLPTR) or Holding Register; (TBLPTR) +1 TBLPTR; if TBLWT*-, (TABLAT) Prog Mem (TBLPTR) or Holding Register; (TBLPTR) -1 TBLPTR; if TBLWT+*, (TBLPTR) +1 TBLPTR; (TABLAT) Prog Mem (TBLPTR) or Holding Register; None 0000 0000 0000 11nn nn=0 * =1 *+ =2 *=3 +* TBLWT (Cont.) Example 1: TBLWT *+; TBLWT ( *; *+; *-; +*) Before Instruction TABLAT TBLPTR MEMORY(00A356h) TABLAT TBLPTR MEMORY(00A356h) = = = = = = +*; 55h 00A356h 0FFh 55h 00A357h 55h After Instructions (table write completion) Example 2: TBLWT Before Instruction TABLAT TBLPTR MEMORY(01389Ah) MEMORY(01389Bh) TABLAT TBLPTR MEMORY(01389Ah) MEMORY(01389Bh) = = = = = = = = 34h 01389Ah 0FFh 0FFh 34h 01389Bh 0FFh 34h After Instruction (table write completion) Status Affected: Encoding: Description: This instruction is used to program the contents of Program Memory (P.M.). The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2 MByte address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = 0:Least Significant Byte of Program Memory Word TBLPTR[0] = 1:Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: * no change * post-increment * post-decrement * pre-increment Words: Cycles: Q Cycle Activity: Q1 Decode 1 2 (many if long write is to on-chip EPROM program memory) Q2 No operation Q3 No operation Q4 No operation No operation No No operation No operation (Read operation (Write to Holding TABLAT) Register or Memory) DS39541A-page 256 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 TSTFSZ Syntax: Operands: Operation: Status Affected: Encoding: Description: Test f, skip if 0 [ label ] TSTFSZ f [,a] 0 f 255 a [0,1] skip if f = 0 None 0110 011a ffff ffff XORLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Exclusive OR literal with WREG [ label ] XORLW k 0 k 255 (WREG) .XOR. k WREG N,Z 0000 1010 kkkk kkkk If 'f' = 0, the next instruction, fetched during the current instruction execution, is discarded and a NOP is executed, making this a two-cycle instruction. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction Q2 Read register 'f' The contents of WREG are XOR'ed with the 8-bit literal 'k'. The result is placed in WREG. 1 1 Q3 Process Data Words: Cycles: Q Cycle Activity: Q1 Q2 Decode Read literal 'k' Q4 Write to WREG Words: Cycles: Example: WREG N Z WREG N Z = = = = = = XORLW 0AFh 0B5h ? ? 1Ah 0 0 Before Instruction Q Cycle Activity: Q1 Decode Q3 Process Data Q4 No operation After Instruction If skip: Q1 No operation Q2 No operation Q3 No operation Q4 No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No operation No operation No operation No operation HERE NZERO ZERO Q4 No operation No operation No operation No operation TSTFSZ : : CNT Example: Before Instruction PC = = = = Address (HERE) 00h, Address (ZERO) 00h, Address (NZERO) After Instruction If CNT PC If CNT PC 2001 Microchip Technology Inc. Advance Information DS39541A-page 257 PIC18C601/801 XORWF Syntax: Operands: Exclusive OR WREG with f [ label ] XORWF 0 f 255 d [0,1] a [0,1] (WREG) .XOR. (f) dest N,Z 0001 10da ffff ffff f [,d [,a]] Operation: Status Affected: Encoding: Description: Exclusive OR the contents of WREG with register 'f'. If 'd' is 0, the result is stored in WREG. If 'd' is 1, the result is stored back in the register 'f' (default). If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1 Q3 Process Data Words: Cycles: Q Cycle Activity: Q1 Q2 Decode Read register 'f' Q4 Write to destination Example: REG WREG N Z REG WREG N Z = = = = = = = = XORWF 0AFh 0B5h ? ? 1Ah 0B5h 0 0 REG Before Instruction After Instruction DS39541A-page 258 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 21.0 DEVELOPMENT SUPPORT The MPLAB IDE allows you to: * Edit your source files (either assembly or `C') * One touch assemble (or compile) and download to PICmicro emulator and simulator tools (automatically updates all project information) * Debug using: - source files - absolute listing file - machine code The ability to use MPLAB IDE with multiple debugging tools allows users to easily switch from the costeffective simulator to a full-featured emulator with minimal retraining. The PICmicro(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C17 and MPLAB C18 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - ICEPICTM In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD for PIC16F87X * Device Programmers - PRO MATE(R) II Universal Device Programmer - PICSTART(R) Plus Entry-Level Development Programmer * Low Cost Demonstration Boards - PICDEMTM 1 Demonstration Board - PICDEM 2 Demonstration Board - PICDEM 3 Demonstration Board - PICDEM 17 Demonstration Board - KEELOQ(R) Demonstration Board 21.2 MPASM Assembler The MPASM assembler is a full-featured universal macro assembler for all PICmicro MCU's. The MPASM assembler has a command line interface and a Windows shell. It can be used as a stand-alone application on a Windows 3.x or greater system, or it can be used through MPLAB IDE. The MPASM assembler generates relocatable object files for the MPLINK object linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, an absolute LST file that contains source lines and generated machine code, and a COD file for debugging. The MPASM assembler features include: * Integration into MPLAB IDE projects. * User-defined macros to streamline assembly code. * Conditional assembly for multi-purpose source files. * Directives that allow complete control over the assembly process. 21.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8-bit microcontroller market. The MPLAB IDE is a Windows(R)-based application that contains: * An interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) * A full-featured editor * A project manager * Customizable toolbar and key mapping * A status bar * On-line help 21.3 MPLAB C17 and MPLAB C18 C Compilers The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI `C' compilers for Microchip's PIC17CXXX and PIC18CXXX family of microcontrollers, respectively. These compilers provide powerful integration capabilities and ease of use not found with other compilers. For easier source level debugging, the compilers provide symbol information that is compatible with the MPLAB IDE memory display. 2001 Microchip Technology Inc. Advance Information DS39541A-page 259 PIC18C601/801 21.4 MPLINK Object Linker/ MPLIB Object Librarian 21.6 MPLAB ICE High Performance Universal In-Circuit Emulator with MPLAB IDE The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can also link relocatable objects from pre-compiled libraries, using directives from a linker script. The MPLIB object librarian is a librarian for precompiled code to be used with the MPLINK object linker. When a routine from a library is called from another source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The MPLIB object librarian manages the creation and modification of library files. The MPLINK object linker features include: * Integration with MPASM assembler and MPLAB C17 and MPLAB C18 C compilers. * Allows all memory areas to be defined as sections to provide link-time flexibility. The MPLIB object librarian features include: * Easier linking because single libraries can be included instead of many smaller files. * Helps keep code maintainable by grouping related modules together. * Allows libraries to be created and modules to be added, listed, replaced, deleted or extracted. The MPLAB ICE universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers (MCUs). Software control of the MPLAB ICE in-circuit emulator is provided by the MPLAB Integrated Development Environment (IDE), which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the MPLAB ICE in-circuit emulator allows expansion to support new PICmicro microcontrollers. The MPLAB ICE in-circuit emulator system has been designed as a real-time emulation system, with advanced features that are generally found on more expensive development tools. The PC platform and Microsoft(R) Windows environment were chosen to best make these features available to you, the end user. 21.7 ICEPIC In-Circuit Emulator 21.5 MPLAB SIM Software Simulator The MPLAB SIM software simulator allows code development in a PC-hosted environment by simulating the PICmicro series microcontrollers on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user-defined key press, to any of the pins. The execution can be performed in single step, execute until break, or trace mode. The MPLAB SIM simulator fully supports symbolic debugging using the MPLAB C17 and the MPLAB C18 C compilers and the MPASM assembler. The software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent multiproject software development tool. The ICEPIC low cost, in-circuit emulator is a solution for the Microchip Technology PIC16C5X, PIC16C6X, PIC16C7X and PIC16CXXX families of 8-bit OneTime-Programmable (OTP) microcontrollers. The modular system can support different subsets of PIC16C5X or PIC16CXXX products through the use of interchangeable personality modules, or daughter boards. The emulator is capable of emulating without target application circuitry being present. DS39541A-page 260 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 21.8 MPLAB ICD In-Circuit Debugger Microchip's In-Circuit Debugger, MPLAB ICD, is a powerful, low cost, run-time development tool. This tool is based on the FLASH PIC16F87X and can be used to develop for this and other PICmicro microcontrollers from the PIC16CXXX family. The MPLAB ICD utilizes the in-circuit debugging capability built into the PIC16F87X. This feature, along with Microchip's In-Circuit Serial ProgrammingTM protocol, offers costeffective in-circuit FLASH debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by watching variables, singlestepping and setting break points. Running at full speed enables testing hardware in real-time. 21.11 PICDEM 1 Low Cost PICmicro Demonstration Board The PICDEM 1 demonstration board is a simple board which demonstrates the capabilities of several of Microchip's microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The user can program the sample microcontrollers provided with the PICDEM 1 demonstration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer, and easily test firmware. The user can also connect the PICDEM 1 demonstration board to the MPLAB ICE incircuit emulator and download the firmware to the emulator for testing. A prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push button switches and eight LEDs connected to PORTB. 21.9 PRO MATE II Universal Device Programmer The PRO MATE II universal device programmer is a full-featured programmer, capable of operating in stand-alone mode, as well as PC-hosted mode. The PRO MATE II device programmer is CE compliant. The PRO MATE II device programmer has programmable VDD and VPP supplies, which allow it to verify programmed memory at VDD min and VDD max for maximum reliability. It has an LCD display for instructions and error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In stand-alone mode, the PRO MATE II device programmer can read, verify, or program PICmicro devices. It can also set code protection in this mode. 21.12 PICDEM 2 Low Cost PIC16CXX Demonstration Board The PICDEM 2 demonstration board is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM 2 demonstration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer, and easily test firmware. The MPLAB ICE in-circuit emulator may also be used with the PICDEM 2 demonstration board to test firmware. A prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push button switches, a potentiometer for simulated analog input, a serial EEPROM to demonstrate usage of the I2CTM bus and separate headers for connection to an LCD module and a keypad. 21.10 PICSTART Plus Entry Level Development Programmer The PICSTART Plus development programmer is an easy-to-use, low cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus development programmer supports all PICmicro devices with up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus development programmer is CE compliant. 2001 Microchip Technology Inc. Advance Information DS39541A-page 261 PIC18C601/801 21.13 PICDEM 3 Low Cost PIC16CXXX Demonstration Board The PICDEM 3 demonstration board is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with an LCD Module. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM 3 demonstration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer with an adapter socket, and easily test firmware. The MPLAB ICE in-circuit emulator may also be used with the PICDEM 3 demonstration board to test firmware. A prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM 3 demonstration board is a LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature and day of the week. The PICDEM 3 demonstration board provides an additional RS-232 interface and Windows software for showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals. 21.14 PICDEM 17 Demonstration Board The PICDEM 17 demonstration board is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers, including PIC17C752, PIC17C756A, PIC17C762 and PIC17C766. All necessary hardware is included to run basic demo programs, which are supplied on a 3.5-inch disk. A programmed sample is included and the user may erase it and program it with the other sample programs using the PRO MATE II device programmer, or the PICSTART Plus development programmer, and easily debug and test the sample code. In addition, the PICDEM 17 demonstration board supports downloading of programs to and executing out of external FLASH memory on board. The PICDEM 17 demonstration board is also usable with the MPLAB ICE in-circuit emulator, or the PICMASTER emulator and all of the sample programs can be run and modified using either emulator. Additionally, a generous prototype area is available for user hardware. 21.15 KEELOQ Evaluation and Programming Tools KEELOQ evaluation and programming tools support Microchip's HCS Secure Data Products. The HCS evaluation kit includes a LCD display to show changing codes, a decoder to decode transmissions and a programming interface to program test transmitters. DS39541A-page 262 Advance Information 2001 Microchip Technology Inc. 24CXX/ 25CXX/ 93CXX PIC14000 HCSXXX PIC16C5X PIC16C6X PIC16C7X PIC16C8X PIC17C4X PIC16F62X PIC16C7XX PIC16F8XX PIC16C9XX PIC17C7XX PIC12CXXX PIC16CXXX PIC18CXX2 MCRFXXX MCP2510 TABLE 21-1: MPLAB(R) Integrated Development Environment a a a a a a a a a a a a aa aa MPLAB(R) C17 C Compiler Software Tools MPLAB(R) C18 C Compiler MPASMTM Assembler/ MPLINKTM Object Linker a a Programmers Debugger Emulators Demo Boards and Eval Kits 2001 Microchip Technology Inc. aaa aa ** aa aa aa aa aa aa aa aa aa aa aa aa MPLAB(R) ICE In-Circuit Emulator ICEPICTM In-Circuit Emulator a * * a a a a a a a MPLAB(R) ICD In-Circuit Debugger a ** a a PICSTART(R) Plus Entry Level Development Programmer a ** a a a a a a a a a a a a a PRO MATE(R) II Universal Device Programmer a a a a a a a a a a a a a a a a PICDEMTM 1 Demonstration Board a a a a a DEVELOPMENT TOOLS FROM MICROCHIP Advance Information a a a a PICDEMTM 2 Demonstration Board a PICDEMTM 3 Demonstration Board PICDEMTM 14A Demonstration Board PICDEMTM 17 Demonstration Board a KEELOQ(R) Evaluation Kit aa KEELOQ(R) Transponder Kit microIDTM Programmer's Kit aa 125 kHz microIDTM Developer's Kit 125 kHz Anticollision microIDTM Developer's Kit a 13.56 MHz Anticollision microIDTM Developer's Kit a PIC18C601/801 DS39541A-page 263 MCP2510 CAN Developer's Kit * Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB(R) ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77. ** Contact Microchip Technology Inc. for availability date. Development tool is available on select devices. a PIC18C601/801 NOTES: DS39541A-page 264 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 22.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings() Ambient temperature under bias.............................................................................................................-55C to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) ......................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V Voltage on RA4 with respect to VSS............................................................................................................... 0V to +8.5V Total power dissipation (Note 1) ...............................................................................................................................1.0W Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin ..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. 20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by all ports (combined) ....................................................................................................200 mA Maximum current sourced by all ports (combined) ...............................................................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x IOL) 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR/VPP pin, rather than pulling this pin directly to VSS. NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2001 Microchip Technology Inc. Advance Information DS39541A-page 265 PIC18C601/801 FIGURE 22-1: PIC18C601/801 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0 V 5.5 V 5.0 V PIC18C601/801 4.2V Voltage 4.5 V 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V 25 MHz Frequency FIGURE 22-2: PIC18C601/801 VOLTAGE-FREQUENCY GRAPH (EXTENDED) 6.0 V 5.5 V 5.0 V PIC18C601/801 4.2V Voltage 4.5 V 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V 4 MHz 16 MHz 25 MHz Frequency FMAX = (12.0 MHz/V) (VDDAPPMIN - 2.0 V) + 4 MHz where VDDAPPMIN < 3 FMAX = (7.5 MHz/V) (VDDAPPMIN - 3.0 V) + 16 MHz where VDDAPPMIN > 3 Note: VDDAPP is the minimum voltage of the PICmicro(R) device in the application. DS39541A-page 266 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 22.1 DC Characteristics Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Characteristic/ Device Supply Voltage PIC18LC601/801 D001 D002 D003 VDR VPOR PIC18C601/801 RAM Data Retention Voltage(1) VDD Start Voltage to ensure internal Power-on Reset signal VDD Rise Rate to ensure internal Poweron Reset signal 2.0 4.2 1.5 -- -- -- -- -- 5.5 5.5 -- 0.7 V V V V See section on Power-on Reset for details Min Typ Max Units Conditions PIC18LC601/801 (Industrial) PIC18C601/801 (Industrial, Extended) Param No. D001 Symbol VDD D004 SVDD 0.05 -- -- V/ms See section on Power-on Reset for details Legend: Rows with industrial-extended data are shaded for improved readability. Note 1: This is the limit to which VDD can be lowered in SLEEP mode, or during a device RESET, without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, ...). 4: For RC osc option, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. 2001 Microchip Technology Inc. Advance Information DS39541A-page 267 PIC18C601/801 22.1 DC Characteristics (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Characteristic/ Device Supply Current(2,4) PIC18LC601/801 -- D010 D010A D010A D010C D010C D013 PIC18C601/801 -- PIC18LC601/801 -- PIC18C601/801 -- PIC18LC601/801 -- PIC18C601/801 -- PIC18LC601/801 -- -- -- D013 PIC18C601/801 -- -- D014 PIC18LC601/801 -- -- D014 PIC18C601/801 -- -- -- -- TBD TBD A A -- -- 48 TBD A A -- -- 50 50 mA mA -- -- -- TBD 50 50 mA mA mA -- 45 mA TBD 45 mA TBD TBD A TBD TBD A TBD TBD mA TBD TBD mA RC osc option FOSC = 4 MHz, VDD = 2.5V RC osc options FOSC = 4 MHz, VDD = 4.2V LP osc option FOSC = 32 kHz, VDD = 2.5V LP osc option FOSC = 32 kHz, VDD = 4.2V EC osc option, FOSC = 25 MHz, VDD = 5.5V EC osc option, FOSC = 25 MHz, VDD = 5.5V HS osc options FOSC = 6 MHz, VDD = 2.5V FOSC = 25 MHz, VDD = 5.5V HS + PLL osc option FOSC = 10 MHz, VDD = 5.5V HS osc option FOSC = 25 MHz, VDD = 5.5V HS + PLL osc option FOSC = 10 MHz, VDD = 5.5V Timer1 osc option FOSC = 32 kHz, VDD = 2.5V FOSC = 32 kHz, VDD = 2.5V, 25C OSCB osc option FOSC = 32 kHz, VDD = 4.2V FOSC = 32 kHz, VDD = 4.2V, 25C Min Typ Max Units Conditions PIC18LC601/801 (Industrial) PIC18C601/801 (Industrial, Extended) Param No. D010 Symbol IDD Legend: Rows with industrial-extended data are shaded for improved readability. Note 1: This is the limit to which VDD can be lowered in SLEEP mode, or during a device RESET, without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, ...). 4: For RC osc option, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. DS39541A-page 268 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 22.1 DC Characteristics (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Characteristic/ Device Power-down Current(3) PIC18LC601/801 -- -- -- -- -- -- -- -- IWDT Module Differential Current PIC18LC801/601 Watchdog Timer -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TBD 6.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TBD 12 TBD TBD TBD TBD TBD 50 TBD TBD TBD TBD 3 TBD TBD TBD TBD A A A A A A A A A A A A A A A A A VDD = 2.5V VDD = 3.0V VDD = 5.5V VDD = 2.5V, 25C VDD = 5.5V, -40C to +85C VDD = 5.5V, -40C to +125C VDD = 4.2V, 25C VDD = 2.5V VDD = 2.5V, 25C VDD = 4.2V, -40C to +85C VDD = 4.2V, -40C to +125C VDD = 4.2V, 25C VDD = 2.5V VDD = 2.5V, 25C VDD = 4.2V, -40C to +85C VDD = 4.2V, -40C to +125C VDD = 4.2V, 25C TBD -- -- TBD -- -- TBD -- 5 36 TBD TBD 36 TBD TBD 42 A A A A A A A VDD = 2.5V, -40C to +85C VDD = 5.5V, -40C to +85C VDD = 2.5V, 25C VDD = 4.2V, -40C to +85C VDD = 5.5V, -40C to +85C VDD = 4.2V, 25C VDD = 4.2V, -40C to +125C VDD = 5.5V, -40C to +125C Min Typ Max Units Conditions PIC18LC601/801 (Industrial) PIC18C601/801 (Industrial, Extended) Param No. D020 Symbol IPD D020 D020A D021B D022 PIC18C601/801 D022 PIC18C601/801 Watchdog Timer ILVD PIC18LC801/601 Low Voltage Detect PIC18C601/801 Low Voltage Detect IOSCB PIC18LC801/601 Timer1 Oscillator PIC18C601/801 Timer1 Oscillator D022B D022B D025 D025 Legend: Rows with industrial-extended data are shaded for improved readability. Note 1: This is the limit to which VDD can be lowered in SLEEP mode, or during a device RESET, without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, ...). 4: For RC osc option, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. 2001 Microchip Technology Inc. Advance Information DS39541A-page 269 PIC18C601/801 22.2 DC Characteristics: PIC18C801 (Industrial, Extended) PIC18LC601/801 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min Max Units Conditions DC CHARACTERISTICS Param Symbol Characteristic/ No. Device Input Low Voltage VIL I/O ports: D030 with TTL buffer VSS D030A -- D031 with Schmitt Trigger buffer VSS VSS RC3 and RC4 VSS D032 MCLR D032A OSC1 (in XT, HS and LP modes) VSS and T1OSI VSS D033 OSC1(in RC mode)(1) VIH Input High Voltage I/O ports: D040 with TTL buffer 0.25VDD + 0.8V D040A 2.0 D041 with Schmitt Trigger buffer 0.8VDD 0.7VDD RC3 and RC4 0.8VDD D042 MCLR D042A OSC1 (in HS and LP modes) and 0.7VDD T1OSI 0.9VDD D043 OSC1 (RC mode)(1) VHYS Hysteresis of Schmitt Trigger Inputs D050 TBD (2,3) IIL Input Leakage Current D060 I/O ports -- D061 D063 0.15VDD 0.8 0.2 VDD 0.3VDD 0.2 VDD 0.3VDD 0.2 VDD V V V V V V V VDD < 4.5V 4.5V VDD 5.5V VDD VDD VDD VDD VDD VDD VDD TBD 1 V V V V V V V V A VDD < 4.5V 4.5V VDD 5.5V -- 5 A MCLR OSC1 -- 5 A IPU Weak Pull-up Current D070 IPURB PORTB weak pull-up current 50 400 A VDD = 5V, VPIN = VSS Note 1: In RC oscillator option, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PICmicro device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. VSS VPIN VDD, Pin at hi-impedance Vss VPIN VDD Vss VPIN VDD DS39541A-page 270 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 22.2 DC Characteristics: PIC18C801 (Industrial, Extended) PIC18LC601/801 (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min Max Units Conditions DC CHARACTERISTICS Param Symbol Characteristic/ No. Device VOL Output Low Voltage D080 I/O ports D080A D083 D083A D084 D084A D085 D085A VOH D090 D090A D092 D092A D093 D093A D094 D094A VOD D150 Open-drain High Voltage Control Signals System Bus mode OSC2/CLKO (RC mode) Output High Voltage(3) I/O ports Control Signals System Bus mode OSC2/CLKO (RC mode) -- -- -- -- -- -- -- -- 0.6 0.6 0.6 0.6 TBD TBD TBD TBD V V V V V V V V IOL = 8.5 mA, VDD = 4.5V, -40C to +85C IOL = 7.0 mA, VDD = 4.5V, -40C to +125C IOL = 1.6 mA, VDD = 4.5V, -40C to +85C IOL = 1.2 mA, VDD = 4.5V, -40C to +125C IOL = 1.6 mA, VDD = 4.5V, -40C to +85C IOL = 1.2 mA, VDD = 4.5V, -40C to +125C IOL = 1.6 mA, VDD = 4.5V, -40C to +85C IOL = 1.2 mA, VDD = 4.5V, -40C to +125C IOH = -3.0 mA, VDD = 4.5V, -40C to +85C IOH = -2.5 mA, VDD = 4.5V, -40C to +125C IOH = -1.3 mA, VDD = 4.5V, -40C to +85C IOH = -1.0 mA, VDD = 4.5V, -40C to +125C IOH = -1.3 mA, VDD = 4.5V, -40C to +85C IOH = -1.0 mA, VDD = 4.5V, -40C to +125C IOH = -1.3 mA, VDD = 4.5V, -40C to +85C IOH = -1.0 mA, VDD = 4.5V, -40C to +125C VDD - 0.7 VDD - 0.7 VDD - 0.7 VDD - 0.7 TBD TBD TBD TBD -- -- -- -- -- -- -- -- V V V V V V V V -- 7.5 V RA4 pin Capacitive Loading Specs on Output Pins D101 CIO All I/O pins and OSC2 -- 50 pF To meet the AC Timing (in RC mode) Specifications D102 CB SCL, SDA -- 400 pF In I2C mode Note 1: In RC oscillator option, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PICmicro device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 2001 Microchip Technology Inc. Advance Information DS39541A-page 271 PIC18C601/801 FIGURE 22-3: LOW-VOLTAGE DETECT CHARACTERISTICS VDD (LVDIF can be cleared in software) VLVD (LVDIF set by hardware) LVDIF TABLE 22-1: LOW VOLTAGE DETECT CHARACTERISTICS VCC = 2.0V to 5.5V Commercial (C): TAMB = 0C to +70C Industrial (I): TAMB = -40C to +85C Param No. D420 Characteristic LVD Voltage on VDD Transition High to Low Symbol Min Typ Max Units Conditions LVV = 0001 VLVD 2.0 2.06 2.12 V LVV = 0010 2.2 2.27 2.34 V LVV = 0011 2.4 2.47 2.54 V LVV = 0100 2.5 2.58 2.66 V LVV = 0101 2.7 2.78 2.86 V LVV = 0110 2.8 2.89 2.98 V LVV = 0111 3.0 3.1 3.2 V LVV = 1000 3.3 3.41 3.52 V LVV = 1001 3.5 3.61 3.72 V LVV = 1010 3.6 3.72 3.84 V LVV = 1011 3.8 3.92 4.04 V LVV = 1100 4.0 4.13 4.26 V LVV = 1101 4.2 4.33 4.46 V LVV = 1110 4.5 4.64 4.78 V D421 LVD Voltage Drift Temperature TCVOUT -- 15 50 ppm/C Coefficient VBG/ D422 Bandgap Voltage Drift with respect to -- -- 50 V/V VDD Regulation VDD D423 Bandgap Reference Voltage Value VBG -- 1.22 V Note: Production tested at TAMB = 25C. Specifications over temperature limits guaranteed by characterization. DS39541A-page 272 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 22.3 22.3.1 AC (Timing) Characteristics TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKO cs CS di SDI do SDO dt Data-in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low I2C only AA output access BUF Bus free TCC:ST (I2C specifications only) CC HD Hold ST DAT DATA input hold STA START condition 3. TCC:ST 4. Ts T (I2C specifications only) (I2C specifications only) Time osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCK SS T0CKI T1CKI WR P R V Z High Low Period Rise Valid Hi-impedance High Low SU STO Setup STOP condition 2001 Microchip Technology Inc. Advance Information DS39541A-page 273 PIC18C601/801 22.3.2 TIMING CONDITIONS The temperature and voltages specified in Table 22-2 apply to all timing specifications, unless otherwise noted. Figure 22-4 specifies the load conditions for the timing specifications. TABLE 22-2: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Operating voltage VDD range as described in DC spec Section 22.1. LC parts operate for industrial temperatures only. AC CHARACTERISTICS FIGURE 22-4: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load condition 1 VDD/2 CL VSS Pin VSS CL RL = 464 CL = 50 pF for all pins except OSC2/CLKO and including D and E outputs as ports Load condition 2 RL Pin DS39541A-page 274 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 22.3.3 TIMING DIAGRAMS AND SPECIFICATIONS EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 FIGURE 22-5: OSC1 1 2 3 3 4 4 CLKOUT TABLE 22-3: Param No. EXTERNAL CLOCK TIMING REQUIREMENTS Symbol Characteristic FOSC External CLKI Frequency (Note 1) Min Typ Max Units 1 2 3 4 Note 1: DC -- 4 MHz DC -- 25 MHz 4 -- 6.25 MHz DC -- 25 MHz DC -- 200 kHz Oscillator Frequency (Note 1) DC -- 4 MHz 4 -- 25 MHz 4 -- 6.25 MHz 5 -- 200 kHz Tosc External CLKI Period (Note 1) 250 -- -- ns 40 -- -- ns 40 -- -- ns 160 -- -- ns 5 -- -- s Oscillator Period (Note 1) 250 -- -- ns 40 -- 100 ns 160 -- 100 ns 5 -- -- s TCY Instruction Cycle Time (Note 1) 160 TCY DC ns TosL, External Clock in (OSC1) High or 2.5 -- -- s TosH Low Time 10 -- -- ns TosR, External Clock in (OSC1) Rise or -- -- 50 ns TosF Fall Time -- -- 5 ns Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions, with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the "max." cycle time limit is "DC" (no clock) for all devices. TABLE 22-4: Param Symbol No. 7 TPLL CLK PLL CLOCK TIMING SPECIFICATION (VDD = 4.2V - 5.5V) Characteristic PLL Start-up Time (Lock Time) CLKOUT Stability (Jitter) using PLL Min -- -2 Max 2 +2 Units ms % Conditions 2001 Microchip Technology Inc. Advance Information DS39541A-page 275 PIC18C601/801 FIGURE 22-6: CLKOUT AND I/O TIMING Q4 OSC1 10 CLKOUT 13 14 I/O Pin (input) 17 I/O Pin (output) old value 20, 21 Note: Refer to Figure 22-4 for load conditions. 15 new value 19 12 18 16 11 Q1 Q2 Q3 TABLE 22-5: Param. No. 10 11 12 13 14 15 16 17 18 18A CLKOUT AND I/O TIMING REQUIREMENTS Characteristic Min Typ Max Units Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (1) (1) (1) (1) (1) (1) (1) Symbol TosH2ckL TosH2ckH TckR TckF TckL2ioV TioV2ckH TckH2ioI TosH2ioV TosH2ioI OSC1 to CLKOUT -- 75 200 OSC1 to CLKOUT -- 75 200 CLKOUT rise time -- 35 100 CLKOUT fall time -- 35 100 CLKOUT to Port out valid -- -- 0.5TCY + 20 Port in valid before CLKOUT 0.25TCY + 25 -- -- Port in hold after CLKOUT 0 -- -- OSC1 (Q1 cycle) to Port out valid -- 50 150 OSC1 (Q2 cycle) PIC18C601/801 100 -- -- to Port input invalid PIC18LC601/801 200 -- -- (I/O in hold time) 19 TioV2osH Port input valid to OSC1 0 -- -- (I/O in setup time) 20 TioR Port output rise PIC18C601/801 -- 10 25 time 20A PIC18LC601/801 -- -- 60 21 TioF Port output fall time PIC18C601/801 -- 10 25 21A PIC18LC601/801 -- -- 60 INT pin high or low time TCY -- -- 22 TINP 23 TRBP RB7:RB4 change INT high or low time TCY -- -- These parameters are asynchronous events, not related to any internal clock edges. Note 1: Measurements are taken in RC mode, where CLKO pin output is 4 x TOSC. DS39541A-page 276 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 FIGURE 22-7: PROGRAM MEMORY READ TIMING DIAGRAM Q1 OSC1 A<19:16> BA0 AD<15:0> Address Address Q2 Q3 Q4 Q1 Q2 Address Data from external Address 150 151 160 155 166 167 168 163 162 161 ALE 164 169 CS1 CS2 or CSIO 171 171A OE 165 Operating Conditions: 2.0V Param No. 150 151 155 160 161 162 163 164 165 166 167 168 169 171 171A CLKOUT AND I/O TIMING REQUIREMENTS Characteristics Address out valid to ALE (address setup time) ALE to address out invalid (address hold time) ALE to OE AD high-Z to OE (bus release to OE) OE to AD driven LS data valid before OE (data setup time) OE to data in invalid (data hold time) ALE pulse width OE pulse width ALE to ALE (cycle time) Address valid to data valid OE to data valid ALE to OE Chip select active to ALE AD valid to chip select active 0.625TCY-10 0.25TCY-20 -- Min 0.25TCY-10 5 10 0 0.125TCY-5 20 0 -- 0.5TCY-5 -- 0.75TCY-25 Typ -- -- 0.125TCY -- -- -- -- TCY 0.5TCY 0.25TCY -- -- -- -- -- Max -- -- -- -- -- -- -- -- -- -- -- 0.5TCY-25 0.625TCY+10 -- 10 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Symbol TadV2alL TalL2adl TalL2oeL TadZ2oeL ToeH2adD TadV2oeH ToeH2adl TalH2alL ToeL2oeH TalH2alH Tacc Toe TalL2oeH TalH2csL TubL2oeH 2001 Microchip Technology Inc. Advance Information DS39541A-page 277 PIC18C601/801 FIGURE 22-8: 8-BIT PROGRAM MEMORY FETCH TIMING DIAGRAM Q1 Q2 Q3 Q4 Q1 Q2 OSC1 A<19:8> Address Address 166 150 151 AD<7:0> Address Data Data 161 Address 162 162A 163 BA0 170 ALE CS1 CS2 or CSIO 170A OE Operating Conditions: 2.0V Param No. 150 151 161 162 162A 163 166 170 170A 8-BIT PROGRAM MEMORY FETCH TIMING REQUIREMENTS Symbol TadV2alL TalL2adl ToeH2adD TadV2oeH TadV2oeH ToeH2adl TalH2alH TubH2oeH TubL2oeH Characteristics Address out valid to ALE (address setup time) ALE to address out invalid (address hold time) OE to AD driven LS data valid before OE (data setup time) MS data valid before OE (data setup time) OE to data in invalid (data hold time) ALE to ALE (cycle time) BA0 = 0 valid before OE BA0 = 1 valid before OE Min 0.25TCY-10 5 0.125TCY-5 20 0.25TCY+20 0 -- 0.25TCY-10 0.5TCY-10 Typ -- -- -- -- -- -- 0.25TCY -- -- Max -- -- -- -- -- -- -- -- -- Units ns ns ns ns ns ns ns ns ns DS39541A-page 278 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 FIGURE 22-9: PROGRAM MEMORY WRITE TIMING DIAGRAM Q1 OSC1 A<19:16> BA0 Q2 Q3 Q4 Q1 Q2 Address Address 166 AD<15:0> Address Data Address 153 150 151 ALE CS1, CS2, or CSIO 154 WRH or WRL UB or LB 157 157A 156 Operating Conditions: 2.0V Param No. 150 151 153 154 156 157 157A 166 36 PROGRAM MEMORY WRITE TIMING REQUIREMENTS Symbol TadV2alL TalL2adl TwrH2adl TwrL Characteristics Address out valid to ALE (address setup time) ALE to address out invalid (address hold time) WRn to data out invalid (data hold time) WRn pulse width Min 0.25TCY-10 5 5 0.5TCY-5 0.5TCY-10 0.25TCY 0.125TCY-5 -- -- Typ -- -- -- 0.5TCY -- -- -- 0.25TCY 20 Max -- -- -- -- -- -- -- -- 50 Units ns ns ns ns ns ns ns ns s TadV2wrH Data valid before WRn (data setup time) TbsV2wrL TwrH2bsI TalH2alH TIVRST Byte select valid before WRn (byte select setup time) WRn to byte select invalid (byte select hold time) ALE to ALE (cycle time) Time for Internal Reference Voltage to become stable 2001 Microchip Technology Inc. Advance Information DS39541A-page 279 PIC18C601/801 FIGURE 22-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR Internal POR 33 PWRT Time-out OSC Time-out Internal Reset Watchdog Timer Reset 34 I/O Pins Note: Refer to Figure 22-4 for load conditions. 32 30 31 34 TABLE 22-9: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Oscillation Start-up Timer Period Power up Timer Period I/O Hi-Impedance from MCLR Low or Watchdog Timer Reset Min 2 7 -- 28 -- Typ -- 18 -- 72 2 Max -- 33 1024TOSC 132 -- Units s ms -- ms s TOSC = OSC1 period Conditions Param. Symbol No. 30 31 32 33 34 TmcL TWDT TOST TPWRT TIOZ DS39541A-page 280 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 FIGURE 22-11: T0CKI TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS 40 41 42 T1OSO/T1CKI 45 46 47 TMR0 or TMR1 Note: Refer to Figure 22-4 for load conditions. 48 TABLE 22-10: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Symbol No. 40 41 42 Tt0H Tt0L Tt0P Characteristic T0CKI High Pulse Width No Prescaler With Prescaler T0CKI Low Pulse Width No Prescaler With Prescaler T0CKI Period No Prescaler With Prescaler Min 0.5TCY + 20 10 0.5TCY + 20 10 TCY + 10 Greater of: 20 nS or TCY + 40 N 0.5TCY + 20 10 25 30 50 0.5TCY + 5 10 25 30 TBD Greater of: 20 nS or TCY + 40 N 60 DC 2TOSC Max -- -- -- -- -- -- Units ns ns ns ns ns ns Conditions N = prescale value (1, 2, 4,..., 256) 45 Tt1H T1CKI High Time 46 Tt1L T1CKI Low Time 47 Tt1P T1CKI input period Synchronous, no prescaler Synchronous, PIC18C601/801 with prescaler PIC18LC601/801 Asynchronous PIC18C601/801 PIC18LC601/801 Synchronous, no prescaler Synchronous, PIC18C601/801 with prescaler PIC18LC601/801 Asynchronous PIC18C601/801 PIC18LC601/801 Synchronous -- -- -- -- -- -- -- -- -- TBD -- ns ns ns ns ns ns ns ns ns ns ns N = prescale value (1, 2, 4, 8) 48 Asynchronous Ft1 T1CKI oscillator input frequency range Tcke2tmrI Delay from external T1CKI clock edge to timer increment -- 50 7TOSC ns kHz -- 2001 Microchip Technology Inc. Advance Information DS39541A-page 281 PIC18C601/801 FIGURE 22-12: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) CCPx (Capture mode) 50 52 51 CCPx (Compare or PWM mode) 53 Note: Refer to Figure 22-4 for load conditions. 54 TABLE 22-11: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2) Param. Symbol No. 50 TccL Characteristic CCPx input low No Prescaler time With PIC18C601/801 Prescaler PIC18LC601/801 CCPx input high No Prescaler time With PIC18C601/801 Prescaler PIC18LC601/801 CCPx input period CCPx output fall time CCPx output fall time PIC18C601/801 PIC18LC601/801 PIC18C601/801 PIC18LC601/801 Min 0.5TCY + 20 10 20 0.5TCY + 20 10 20 3TCY + 40 N -- -- -- -- Max -- -- -- -- -- -- -- 25 45 25 45 Units ns ns ns ns ns ns ns ns ns ns ns Conditions 51 TccH 52 53 54 TccP TccR TccF N = prescale value (1, 4 or 16) DS39541A-page 282 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 FIGURE 22-13: SS 70 SCK (CKP = 0) 71 72 78 SCK (CKP = 1) 79 78 79 EXAMPLE SPI MASTER MODE TIMING (CKE = 0) 80 SDO MSb 75, 76 SDI MSb In 74 73 Note: Refer to Figure 22-4 for load conditions. Bit6 - - - -1 Bit6 - - - - - -1 LSb LSb In TABLE 22-12: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) Param. No. 70 71 71A 72 72A 73 73A 74 75 76 78 79 80 TdiV2scH, TdiV2scL TB2B TscH2diL, TscL2diL TdoR TdoF TscR TscF TscH2doV, TscL2doV TscL Symbol TssL2scH, TssL2scL TscH Characteristic SS to SCK or SCK input SCK input high time (Slave mode) SCK input low time (Slave mode) Continuous Single Byte Continuous Single Byte Min TCY 1.25TCY + 30 40 1.25TCY + 30 40 100 1.5TCY + 40 100 -- -- -- PIC18C601/801 PIC18LC601/801 PIC18C601/801 PIC18LC601/801 -- -- -- -- -- Max Units -- -- -- -- -- -- -- -- 25 45 25 25 45 25 50 100 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Note 2) (Note 1) (Note 1) Conditions Setup time of SDI data input to SCK edge Last clock edge of Byte1 to the 1st clock edge of Byte2 Hold time of SDI data input to SCK edge SDO data output rise time SDO data output fall time SCK output rise time (Master mode) PIC18C601/801 PIC18LC601/801 SCK output fall time (Master mode) SDO data output valid after SCK edge Note 1: Requires the use of parameter # 73A. 2: Only if parameter #s 71A and 72A are used. 2001 Microchip Technology Inc. Advance Information DS39541A-page 283 PIC18C601/801 FIGURE 22-14: SS 81 SCK (CKP = 0) 71 73 SCK (CKP = 1) 80 78 72 79 EXAMPLE SPI MASTER MODE TIMING (CKE = 1) SDO MSb 75, 76 Bit6 - - - - - -1 LSb SDI MSb In 74 Bit6 - - - -1 LSb In Note: Refer to Figure 22-4 for load conditions. TABLE 22-13: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param. No. 71 71A 72 72A 73 73A 74 75 76 78 Symbol TscH TscL TdiV2scH, TdiV2scL TB2B TscH2diL, TscL2diL TdoR TdoF TscR Characteristic Continuous Single Byte SCK input low time Continuous (Slave mode) Single Byte Setup time of SDI data input to SCK edge Last clock edge of Byte1 to the 1st clock edge of Byte2 Hold time of SDI data input to SCK edge SDO data output rise time SDO data output fall time SCK output rise time (Master mode) PIC18C601/801 PIC18LC601/801 SCK input high time (Slave mode) Min 1.25TCY + 30 40 1.25TCY + 30 40 100 1.5TCY + 40 100 -- -- -- -- -- -- -- -- TCY Max Units -- -- -- -- -- -- -- 25 45 25 25 45 25 50 100 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Conditions (Note 1) (Note 1) (Note 2) PIC18C601/801 PIC18LC601/801 79 TscF SCK output fall time (Master mode) 80 TscH2doV, SDO data output valid after PIC18C601/801 TscL2doV SCK edge PIC18LC601/801 81 TdoV2scH, SDO data output setup to SCK edge TdoV2scL Note 1: Requires the use of parameter # 73A. 2: Only if parameter #s 71A and 72A are used. DS39541A-page 284 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 FIGURE 22-15: SS 70 SCK (CKP = 0) 71 72 83 EXAMPLE SPI SLAVE MODE TIMING (CKE = 0) 78 79 SCK (CKP = 1) 79 78 80 SDO MSb 75, 76 SDI MSb In 74 73 Note: Refer to Figure 22-4 for load conditions. Bit6 - - - -1 Bit6 - - - - - -1 LSb 77 LSb In TABLE 22-14: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0)) Param No. 70 71 71A 72 72A 73 73A 74 75 76 77 78 79 80 83 TscL Symbol Characteristic Min TCY Continuous Single Byte Continuous Single Byte 1.25TCY + 30 40 1.25TCY + 30 40 100 Max Units -- -- -- -- -- -- -- -- 25 45 -- 10 PIC18C601/801 PIC18LC601/801 -- -- 1.5TCY + 40 -- 25 50 25 45 25 50 100 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Note 2) (Note 1) (Note 1) Conditions TssL2scH, SS to SCK or SCK input TssL2scL TscH SCK input high time (Slave mode) SCK input low time (Slave mode) TdiV2scH, Setup time of SDI data input to SCK edge TdiV2scL TB2B TscH2diL, TscL2diL TdoR TdoF TssH2doZ TscR TscF Hold time of SDI data input to SCK edge SDO data output rise time SDO data output fall time SS to SDO output hi-impedance SCK output rise time (Master mode) PIC18C601/801 PIC18LC601/801 Last clock edge of Byte1 to the 1st clock edge of Byte2 1.5TCY + 40 100 -- SCK output fall time (Master mode) TscH2doV, SDO data output valid after SCK PIC18C601/801 TscL2doV edge PIC18LC601/801 TscH2ssH, SS after SCK edge TscL2ssH Note 1: Requires the use of parameter # 73A. 2: Only if parameter #s 71A and 72A are used. 2001 Microchip Technology Inc. Advance Information DS39541A-page 285 PIC18C601/801 FIGURE 22-16: SS EXAMPLE SPI SLAVE MODE TIMING (CKE = 1) 82 SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 SDO MSb 75, 76 Bit6 - - - - - -1 LSb 77 SDI MSb In 74 Bit6 - - - -1 LSb In Note: Refer to Figure 22-4 for load conditions. TABLE 22-15: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param No. 70 71 71A 72 72A 73A 74 75 76 77 78 79 80 Symbol Characteristic Min TCY 1.25TCY + 30 40 1.25TCY + 30 40 1.5TCY + 40 100 -- -- -- 10 -- -- -- -- -- -- -- 1.5TCY + 40 Max Units Conditions -- -- -- -- -- -- -- 25 45 25 50 25 45 25 50 100 50 100 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TssL2scH, SS to SCK or SCK input TssL2scL TscH SCK input high time (Slave mode) TscL TB2B TscH2diL, TscL2diL TdoR TdoF TssH2doZ TscR Continuous Single Byte SCK input low time Continuous (Slave mode) Single Byte Last clock edge of Byte1 to the 1st clock edge of Byte2 Hold time of SDI data input to SCK edge PIC18C601/801 PIC18LC601/801 (Note 1) (Note 1) (Note 2) SDO data output rise time SDO data output fall time SS to SDO output hi-impedance SCK output rise time (Master mode) PIC18C601/801 PIC18LC601/801 TscF SCK output fall time (Master mode) TscH2doV, SDO data output valid after SCK PIC18C601/801 TscL2doV edge PIC18LC601/801 82 TssL2doV SDO data output valid after SS PIC18C601/801 edge PIC18LC601/901 83 TscH2ssH, SS after SCK edge TscL2ssH Note 1: Requires the use of parameter # 73A. 2: Only if parameter #s 71A and 72A are used. DS39541A-page 286 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 FIGURE 22-17: I2C BUS START/STOP BITS TIMING SCL 90 SDA 91 92 93 START Condition Note: Refer to Figure 22-4 for load conditions. STOP Condition TABLE 22-16: I2C BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol No. 90 91 92 93 TSU:STA Characteristic 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode Min 4700 600 4000 600 4700 600 4000 600 Max -- -- -- -- -- -- -- -- Units ns ns ns ns Conditions Only relevant for Repeated START condition After this period, the first clock pulse is generated START condition Setup time THD:STA START condition Hold time TSU:STO STOP condition Setup time THD:STO STOP condition Hold time FIGURE 22-18: I2C BUS DATA TIMING 103 100 101 102 SCL 90 91 106 107 92 SDA In 110 109 109 SDA Out Note: Refer to Figure 22-4 for load conditions. 2001 Microchip Technology Inc. Advance Information DS39541A-page 287 PIC18C601/801 TABLE 22-17: I2C BUS DATA REQUIREMENTS (SLAVE MODE) Param No. 100 Symbol THIGH Characteristic Clock high time 100 kHz mode 400 kHz mode SSP Module 101 TLOW Clock low time 100 kHz mode 400 kHz mode SSP module 102 TR SDA and SCL rise time 100 kHz mode 400 kHz mode Min 4.0 0.6 1.5TCY 4.7 1.3 1.5TCY -- 20 + 0.1Cb -- 20 + 0.1Cb 4.7 0.6 4.0 0.6 0 0 250 100 4.7 0.6 -- -- 4.7 1.3 -- Max -- -- -- -- -- -- 1000 300 300 300 -- -- -- -- -- 0.9 -- -- -- -- 3500 -- -- -- 400 s s ns ns ns ns ns s s s s ns s ns ns s s ns ns s s pF Time the bus must be free before a new transmission can start (Note 1) (Note 2) Cb is specified to be from 10 to 400 pF Only relevant for Repeated START condition After this period the first clock pulse is generated Cb is specified to be from 10 to 400 pF PIC18C601/801 must operate at a minimum of 1.5 MHz PIC18C601/801 must operate at a minimum of 10 MHz Units s s Conditions PIC18C601/801 must operate at a minimum of 1.5 MHz PIC18C601/801 must operate at a minimum of 10 MHz 103 TF SDA and SCL fall time 100 kHz mode 400 kHz mode 90 91 106 107 92 109 110 TSU:STA THD:STA THD:DAT TSU:DAT TSU:STO TAA TBUF START condition setup time 100 kHz mode 400 kHz mode START condition hold 100 kHz mode time 400 kHz mode Data input hold time 100 kHz mode 400 kHz mode Data input setup time 100 kHz mode 400 kHz mode STOP condition setup 100 kHz mode time 400 kHz mode Output valid from clock Bus free time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode D102 Note 1: 2: Cb Bus capacitive loading As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. A fast mode I2C bus device can be used in a standard mode I2C bus system, but the requirement tsu;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line. Before the SCL line is released, TR max. + tsu;DAT = 1000 + 250 = 1250 ns (according to the standard mode I2C bus specification). DS39541A-page 288 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 FIGURE 22-19: MASTER SSP I2C BUS START/STOP BITS TIMING WAVEFORMS SCL 90 SDA 91 92 93 START Condition Note: Refer to Figure 22-4 for load conditions. STOP Condition TABLE 22-18: MASTER SSP I2C BUS START/STOP BITS REQUIREMENTS Param. Symbol No. 90 TSU:STA Characteristic START condition Setup time 91 THD:STA START condition Hold time 92 TSU:STO STOP condition Setup time 93 THD:STO STOP condition Hold time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 1 MHz mode (1) Min 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) Max -- -- -- -- -- -- -- -- -- -- -- -- Units Conditions Only relevant for Repeated START condition After this period, the first clock pulse is generated ns 1 MHz mode(1) 2(TOSC)(BRG + 1) ns 100 kHz mode 400 kHz mode 1 MHz mode (1) ns 100 kHz mode 400 kHz mode 1 MHz mode (1) 2C ns Note 1: Maximum pin capacitance = 10 pF for all I pins. FIGURE 22-20: MASTER SSP I2C BUS DATA TIMING 103 100 101 102 SCL SDA In 90 91 106 107 92 109 109 110 SDA Out Note: Refer to Figure 22-4 for load conditions. 2001 Microchip Technology Inc. Advance Information DS39541A-page 289 PIC18C601/801 TABLE 22-19: MASTER SSP I2C BUS DATA REQUIREMENTS Param Symbol No. 100 THIGH Characteristic Clock high time 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode Min 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) -- 20 + 0.1Cb -- -- 20 + 0.1Cb -- 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 0 0 TBD 250 100 TBD 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) -- -- -- 4.7 1.3 TBD -- Max -- -- -- -- -- -- 1000 300 300 300 300 100 -- -- -- -- -- -- -- 0.9 -- -- -- -- -- -- -- 3500 1000 -- -- -- -- 400 Units ms ms ms ms ms ms ns ns ns ns ns ns ms ms ms ms ms ms ns ms ns ns ns ns ms ms ms ns ns ns ms ms ms pF Time the bus must be free before a new transmission can start (Note 2) Cb is specified to be from 10 to 400 pF Cb is specified to be from 10 to 400 pF Only relevant for Repeated START condition After this period, the first clock pulse is generated Conditions 101 TLOW Clock low time 102 TR SDA and SCL rise time SDA and SCL fall time 103 TF 90 TSU:STA 1 MHz mode(1) START condition 100 kHz mode setup time 400 kHz mode 1 MHz mode(1) START condition 100 kHz mode hold time 400 kHz mode Data input hold time Data input setup time STOP condition setup time 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 91 THD:STA 106 THD:DAT 107 TSU:DAT 92 TSU:STO 109 TAA 1 MHz mode(1) Output valid from 100 kHz mode clock 400 kHz mode Bus free time 1 MHz mode(1) 100 kHz mode 400 kHz mode 110 TBUF D102 Cb 1 MHz mode(1) Bus capacitive loading Note 1: Maximum pin capacitance = 10 pF for all I2C pins. 2: A fast mode I2C bus device can be used in a standard mode I2C bus system, but parameter #107 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line. Before the SCL line is released, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode). DS39541A-page 290 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 FIGURE 22-21: RC6/TX/CK pin RC7/RX/DT pin 120 Note: Refer to Figure 22-4 for load conditions. 122 USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING 121 121 TABLE 22-20: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No. 120 Symbol Characteristic Min Max Units Conditions TckH2dtV SYNC XMIT (Master & Slave) Clock high to data-out valid Tckrf Tdtrf Clock out rise time and fall time (Master mode) Data-out rise time and fall time 121 122 PIC18C601/801 PIC18LC601/801 PIC18C601/801 PIC18LC601/801 PIC18C601/801 PIC18LC601/801 -- -- -- -- -- -- 40 100 20 50 20 50 ns ns ns ns ns ns FIGURE 22-22: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX/CK pin RC7/RX/DT pin 125 126 Note: Refer to Figure 22-4 for load conditions. TABLE 22-21: USART SYNCHRONOUS RECEIVE REQUIREMENTS Param No. 125 126 Symbol TdtV2ckl TckL2dtl Characteristic SYNC RCV (Master & Slave) Data-hold before CK (DT hold time) Data-hold after CK (DT hold time) Min Max Units Conditions 10 15 -- -- ns ns 2001 Microchip Technology Inc. Advance Information DS39541A-page 291 PIC18C601/801 TABLE 22-22: A/D CONVERTER CHARACTERISTICS: PIC18C601/801 (INDUSTRIAL, EXTENDED) PIC18LC601/801 (INDUSTRIAL) Param Symbol No. A01 A03 A04 A05 A06 A10 A20 A20A A21 A22 A25 A30 A40 VREFH VREFL VAIN ZAIN IAD NR EIL EDL EFS EOFF -- VREF Characteristic Resolution Integral linearity error Differential linearity error Full scale error Offset error Monotonicity Reference voltage (VREFH - VREFL) Reference voltage High Reference voltage Low Analog input voltage Recommended impedance of analog voltage source A/D conversion PIC18C601/801 current (VDD) PIC18LC601/801 VREF input current(2) 0 3 AVSS AVSS - 0.3 V AVSS - 0.3 V -- -- -- 10 Min -- -- -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- guaranteed(3) -- -- -- -- -- -- 180 90 -- -- -- AVDD + 0.3 V AVDD VREF + 0.3 V 10.0 -- -- 1000 Max 10 TBD <1 TBD <1 TBD <1 TBD <1 TBD Units bit bit Conditions VREF = VDD 3.0V VREF = VDD < 3.0V LSb VREF = VDD 3.0V LSb VREF = VDD < 3.0V LSb VREF = VDD 3.0V LSb VREF = VDD < 3.0V LSb VREF = VDD 3.0V LSb VREF = VDD < 3.0V LSb VREF = VDD 3.0V LSb VREF = VDD < 3.0V -- V V V V V k A A A Average current consumption when A/D is on(1) During VAIN acquisition. Based on differential of VHOLD to VAIN. To charge CHOLD, see Section 17.0. During A/D conversion cycle. For 10-bit resolution VSS VAIN VREF A50 IREF -- -- 10 A Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. VREF current is from RA2/AN2/VREF- and RA3/AN3/VREF+ pins or AVDD and AVSS pins, whichever is selected as reference input. 2: Vss VAIN VREF 3: The A/D conversion result either increases or remains constant as the analog input increases. DS39541A-page 292 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 FIGURE 22-23: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) Q4 130 A/D CLK 132 131 A/D DATA 9 8 7 ... ... 2 1 0 ADRES OLD_DATA NEW_DATA ADIF GO SAMPLING STOPPED DONE TCY SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. TABLE 22-23: A/D CONVERSION REQUIREMENTS Param Symbol No. 130 TAD Characteristic A/D clock period PIC18C601/801 PIC18LC601/801 PIC18C601/801 PIC18LC601/801 131 132 135 136 TCNV TACQ TSWC TAMP Conversion time (not including acquisition time)(1) Acquisition time(3) Switching time from convert sample Amplifier settling time(2) Min 1.6 3.0 2.0 3.0 11 15 10 -- 1 Max 20(5) 20 (5) Units s s s s TAD s s s Conditions TOSC based, VREF 3.0V TOSC based, VREF full range A/D RC mode A/D RC mode 6.0 9.0 12 -- -- (Note 4) -- -40C Temp 125C 0C Temp 125C This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 5 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). Note 1: ADRES register may be read on the following TCY cycle. 2: See Section 17.0 for minimum conditions, when input voltage has changed more than 1 LSb. 3: The time for the holding capacitor to acquire the "New" input voltage, when the voltage changes full scale after the conversion (AVDD to AVSS, or AVSS to AVDD). The source impedance (RS) on the input channels is 50. 4: On the next Q4 cycle of the device clock. 5: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider. 2001 Microchip Technology Inc. Advance Information DS39541A-page 293 PIC18C601/801 NOTES: DS39541A-page 294 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 23.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Graphs and Tables are not available at this time. 2001 Microchip Technology Inc. Advance Information DS39541A-page 295 PIC18C601/801 NOTES: DS39541A-page 296 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 24.0 24.1 PACKAGING INFORMATION Package Marking Information 64-Lead TQFP Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN PIC18C601-I/PT 0017017 68-Lead PLCC Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN PIC18C601-I/L 0017017 80-Lead TQFP Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN PIC18C801-I/PT 0017017 Legend: XX...X YY WW NNN Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2001 Microchip Technology Inc. Advance Information DS39541A-page 297 PIC18C601/801 Package Marking Information (Cont'd) 84-Lead PLCC Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN PIC18C801-I/L 0017017 DS39541A-page 298 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 64-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP) E E1 #leads=n1 p D1 D 2 1 B n CH x 45 A c L A1 (F) A2 Number of Pins Pitch Pins per Side Overall Height Molded Package Thickness Standoff Foot Length Footprint (Reference) Foot Angle Overall Width Overall Length Molded Package Width Molded Package Length Lead Thickness Lead Width Pin 1 Corner Chamfer Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic Units Dimension Limits n p n1 A A2 A1 L (F) E D E1 D1 c B CH MIN .039 .037 .002 .018 0 .463 .463 .390 .390 .005 .007 .025 5 5 INCHES NOM 64 .020 16 .043 .039 .006 .024 .039 3.5 .472 .472 .394 .394 .007 .009 .035 10 10 MAX MIN .047 .041 .010 .030 7 .482 .482 .398 .398 .009 .011 .045 15 15 MILLIMETERS* NOM 64 0.50 16 1.00 1.10 0.95 1.00 0.05 0.15 0.45 0.60 1.00 0 3.5 11.75 12.00 11.75 12.00 9.90 10.00 9.90 10.00 0.13 0.18 0.17 0.22 0.64 0.89 5 10 5 10 MAX 1.20 1.05 0.25 0.75 7 12.25 12.25 10.10 10.10 0.23 0.27 1.14 15 15 Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-026 Drawing No. C04-085 2001 Microchip Technology Inc. Advance Information DS39541A-page 299 PIC18C601/801 68-Lead Plastic Leaded Chip Carrier (L) - Square (PLCC) E E1 #leads=n1 D1 D CH2 x 45 n 12 CH1 x 45 A2 A A3 32 c E2 Units Dimension Limits n p B1 B D2 p A1 MIN Number of Pins Pitch Pins per Side n1 Overall Height A .165 .180 Molded Package Thickness A2 .145 .160 Standoff A1 .020 .035 Side 1 Chamfer Height A3 .024 .034 Corner Chamfer 1 CH1 .040 .050 Corner Chamfer (others) CH2 .000 .010 Overall Width E .985 .995 Overall Length D .985 .995 Molded Package Width E1 .950 .958 Molded Package Length D1 .950 .958 Footprint Width E2 .890 .930 Footprint Length D2 .890 .930 c Lead Thickness .008 .013 Upper Lead Width B1 .026 .032 Lower Lead Width B .013 .021 Mold Draft Angle Top 0 10 Mold Draft Angle Bottom 0 10 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-047 Drawing No. C04-049 INCHES* NOM 68 .050 17 .173 .153 .028 .029 .045 .005 .990 .990 .954 .954 .920 .920 .011 .029 .020 5 5 MAX MIN MILLIMETERS NOM 68 1.27 17 4.19 4.39 3.68 3.87 0.51 0.71 0.61 0.74 1.02 1.14 0.00 0.13 25.02 25.15 25.02 25.15 24.13 24.23 24.13 24.23 22.61 23.37 22.61 23.37 0.20 0.27 0.66 0.74 0.33 0.51 0 5 0 5 MAX 4.57 4.06 0.89 0.86 1.27 0.25 25.27 25.27 24.33 24.33 23.62 23.62 0.33 0.81 0.53 10 10 DS39541A-page 300 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 80-Lead Plastic Thin Quad Flatpack (PT) 12x12x1 mm Body, 1.0/0.10 mm Lead Form (TQFP) E E1 #leads=n1 p D1 D B 2 1 n CH x 45 A c L A1 (F) Units Dimension Limits n p n1 A A2 A1 L (F) E D E1 D1 c B CH INCHES NOM 80 .020 20 .043 .039 .004 .024 .039 3.5 .551 .551 .472 .472 .006 .009 .035 10 10 MILLIMETERS* NOM 80 0.50 20 1.00 1.10 0.95 1.00 0.05 0.10 0.45 0.60 1.00 0 3.5 13.75 14.00 13.75 14.00 11.75 12.00 11.75 12.00 0.09 0.15 0.17 0.22 0.64 0.89 5 10 5 10 A2 MIN MAX MIN MAX Number of Pins Pitch Pins per Side Overall Height Molded Package Thickness Standoff Foot Length Footprint (Reference) Foot Angle Overall Width Overall Length Molded Package Width Molded Package Length Lead Thickness Lead Width Pin 1 Corner Chamfer Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic .039 .037 .002 .018 0 .541 .541 .463 .463 .004 .007 .025 5 5 .047 .041 .006 .030 7 .561 .561 .482 .482 .008 .011 .045 15 15 1.20 1.05 0.15 0.75 7 14.25 14.25 12.25 12.25 0.20 0.27 1.14 15 15 Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-026 Drawing No. C04-092 2001 Microchip Technology Inc. Advance Information DS39541A-page 301 PIC18C601/801 84-Lead Plastic Leaded Chip Carrier (L) - Square (PLCC) E E1 #leads=n1 D1 D n 12 CH2 x 45 CH1 x 45 A2 A A3 32 c E2 Units Dimension Limits n p B1 B D2 p A1 MIN Number of Pins Pitch Pins per Side n1 Overall Height A .180 Molded Package Thickness A2 .160 Standoff A1 .035 Side 1 Chamfer Height A3 .034 Corner Chamfer 1 CH1 .050 Corner Chamfer (others) CH2 .010 Overall Width E .995 Overall Length D .995 Molded Package Width E1 .958 Molded Package Length D1 .958 Footprint Width E2 .930 Footprint Length D2 .930 c Lead Thickness .013 Upper Lead Width B1 .032 Lower Lead Width B .021 Mold Draft Angle Top 10 Mold Draft Angle Bottom 10 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-047 Drawing No. C04-093 INCHES* NOM 68 .050 17 .165 .173 .145 .153 .020 .028 .024 .029 .040 .045 .000 .005 .985 .990 .985 .990 .950 .954 .950 .954 .890 .920 .890 .920 .008 .011 .026 .029 .013 .020 0 5 0 5 MAX MIN MILLIMETERS NOM 68 1.27 17 4.19 4.39 3.68 3.87 0.51 0.71 0.61 0.74 1.02 1.14 0.00 0.13 25.02 25.15 25.02 25.15 24.13 24.23 24.13 24.23 22.61 23.37 22.61 23.37 0.20 0.27 0.66 0.74 0.33 0.51 0 5 0 5 MAX 4.57 4.06 0.89 0.86 1.27 0.25 25.27 25.27 24.33 24.33 23.62 23.62 0.33 0.81 0.53 10 10 DS39541A-page 302 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 APPENDIX A: Revision A This is a new data sheet. DATA SHEET REVISION HISTORY APPENDIX B: DEVICE DIFFERENCES The differences between the PIC18C601/801 devices listed in this data sheet are shown in Table B-1. TABLE B-1: Feature DEVICE DIFFERENCES PIC18C601 256K PIC18C801 2M Maximum External Program Memory (Bytes) Data Memory (Bytes) A/D Channels Package Types TQFP PLCC 1.5K 8 64-pin 68-pin 1.5K 12 80-pin 84-pin 2001 Microchip Technology Inc. Advance Information DS39541A-page 303 PIC18C601/801 APPENDIX C: DEVICE MIGRATIONS APPENDIX D: This section is intended to describe the functional and electrical specification differences when migrating between functionally similar devices (such as from a PIC16C74A to a PIC16C74B). Not Applicable MIGRATING FROM OTHER PICmicro DEVICES This discusses some of the issues in migrating from other PICmicro devices to the PIC18CXXX family of devices. D.1 PIC16CXXX to PIC18CXXX See application note AN716. D.2 PIC17CXXX to PIC18CXXX See application note AN726. DS39541A-page 304 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 APPENDIX E: DEVELOPMENT TOOL VERSION REQUIREMENTS This lists the minimum requirements (software/ firmware) of the specified development tool to support the devices listed in this data sheet. MPLAB(R) IDE: MPLAB(R) MPLAB(R) SIMULATOR: ICE 3000: TBD TBD PIC18C601/801 Processor Module: Part Number TBD PIC18C601/801 Device Adapter: Socket Part Number 64-pin TQFP TBD 68-pin PLCC TBD 80-pin TQFP TBD 84-pin PLCC TBD MPLAB(R) ICD: PRO MATE II: PICSTART Plus: MPASMTM Assembler: (R) (R) (R) TBD TBD TBD TBD MPLAB C18 C Compiler: TBD Note: Please read all associated README.TXT files that are supplied with the development tools. These "read me" files will discuss product support and any known limitations. 2001 Microchip Technology Inc. Advance Information DS39541A-page 305 PIC18C601/801 NOTES: DS39541A-page 306 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 INDEX A A/D ................................................................................... 193 A/D Converter Flag (ADIF Bit) ................................. 195 A/D Converter Interrupt, Configuring ....................... 197 ADCON0 Register .......................................... 193, 195 ADCON1 Register .......................................... 193, 194 ADCON2 Register ................................................... 193 ADRES Register ............................................. 193, 195 Analog Port Pins, Configuring ................................. 199 Associated Registers ............................................... 201 Block Diagram ......................................................... 196 Block Diagram, Analog Input Model ........................ 197 Configuring the Module ........................................... 197 Conversion Clock (TAD) ........................................... 199 Conversion Status (GO/DONE Bit) .......................... 195 Conversions ............................................................. 200 Converter Characteristics ............................... 272, 292 Effects of a RESET .................................................. 206 Equations Acquisition Time .............................................. 198 Minimum Charging Time ................................. 198 Operation During SLEEP ......................................... 206 Sampling Requirements .......................................... 198 Sampling Time ......................................................... 198 Special Event Trigger (CCP) .......................... 144, 200 Timing Diagram ....................................................... 293 Absolute Maximum Ratings ............................................. 265 Access Bank ...................................................................... 58 ADCON0 Register ........................................................... 193 GO/DONE Bit .......................................................... 195 Registers ADCON2 (A/D Control 2) ................................. 195 ADCON1 Register .................................................. 193, 194 ADCON2 Register ........................................................... 193 ADDLW ............................................................................ 221 ADDWF ............................................................................ 221 ADDWFC ......................................................................... 222 ADRES Register ..................................................... 193, 195 AKS .................................................................................. 167 Analog-to-Digital Converter. See A/D ANDLW ............................................................................ 222 ANDWF ............................................................................ 223 Assembler MPASM Assembler ................................................. 259 Phase Lock Loop ...................................................... 23 PORTA RA3:RA0 and RA5 Pins .................................. 103 RA4/T0CKI Pin ................................................ 104 PORTB RB3 Pin ........................................................... 106 RB3:RB0 Port Pins .......................................... 106 RB7:RB4 Port Pins .......................................... 105 PORTC .................................................................... 108 PORTD I/O Mode ......................................................... 110 System Bus Mode ........................................... 111 PORTD (In I/O Port Mode) ...................................... 124 PORTE I/O Mode ......................................................... 113 System Bus Mode ........................................... 114 PORTF RF2:RF0 Pins .................................................. 116 RF5:RF3 Pins .................................................. 117 RF7:RF6 Pins .................................................. 117 PORTG I/O Mode ......................................................... 119 System Bus Mode ........................................... 120 PORTH RH3:RH0 Pins (I/O Mode) ............................... 121 RH3:RH0 Pins (System Bus Mode) ................ 122 RH7:RH4 Pins ................................................. 121 PORTJ I/O Mode ......................................................... 124 System Bus Mode ........................................... 125 Simplified PWM Diagram ........................................ 146 SSP (SPI Mode) ...................................................... 153 Timer0 16-bit Mode ..................................................... 128 8-bit Mode ....................................................... 128 Timer1 ..................................................................... 131 16-bit R/W Mode ............................................. 132 Timer2 ..................................................................... 136 Timer3 ..................................................................... 138 16-bit R/W Mode ............................................. 138 USART Asynchronous Receive ................................... 185 Asynchronous Transmit .................................. 183 Watchdog Timer ...................................................... 211 BN ................................................................................... 224 BNC ................................................................................. 225 BNN ................................................................................. 225 BNOV .............................................................................. 226 BNZ ................................................................................. 226 BOV ................................................................................. 229 BRA ................................................................................. 227 BRG ................................................................................. 164 BSF ................................................................................. 227 BSR. See Bank Select Register. BTFSC ............................................................................. 228 BTFSS ............................................................................. 228 BTG ................................................................................. 229 Bus .................................................................................. 176 Bus Collision During a RESTART Condition ................... 175 Bus Collision During a START Condition ........................ 173 Bus Collision During a STOP Condition .......................... 176 BZ .................................................................................... 230 B Bank Select Register ......................................................... 58 Baud Rate Generator ....................................................... 164 Associated Registers ............................................... 179 BC .................................................................................... 223 BCF .................................................................................. 224 BF .................................................................................... 167 Block Diagram ................................................................. 119 Block Diagrams A/D ........................................................................... 196 Baud Rate Generator .............................................. 164 Capture Mode Operation ......................................... 143 Compare Mode Operation ....................................... 144 Interrupt Logic ............................................................ 90 Low Voltage Detect ................................................. 203 MSSP I2C Mode ......................................................... 159 SPI Mode ......................................................... 153 On-Chip Reset Circuit, Simplified .............................. 29 2001 Microchip Technology Inc. Advance Information DS39541A-page 307 PIC18C601/801 C CALL ................................................................................ 230 Capture (CCP Module) .................................................... 142 Block Diagram ......................................................... 143 CCP Pin Configuration ............................................. 142 CCPR1H:CCPR1L Registers ................................... 142 Changing Between Capture Prescalers ................... 143 Software Interrupt .................................................... 143 Timer1 Mode Selection ............................................ 142 Capture/Compare/PWM (CCP) ....................................... 141 Capture Mode. See Capture CCP1 ....................................................................... 142 CCPR1H Register ........................................... 142 CCPR1L Register ............................................ 142 CCP2 ....................................................................... 142 CCPR2H Register ........................................... 142 CCPR2L Register ............................................ 142 Compare Mode. See Compare Interaction of Two CCP Modules ............................. 142 PWM Mode. See PWM Registers Associated with Capture and Compare ........................................... 145 Timer Resources ..................................................... 142 Timing Diagram ....................................................... 282 Chip Select Chip Select 2 (CS2) ................................................... 71 Chip Select I/O (CSIO) ...................................................... 71 Chip Selects Chip Select 1 (CS1) ................................................... 71 Clocking Scheme ............................................................... 46 CLRF ............................................................................... 231 CLRWDT ......................................................................... 231 Code Examples ............................................................... 154 Changing Between Capture Prescalers ................... 143 Clearing RAM Using Indirect Addressing .................. 59 Combination Unlock (Macro) ..................................... 51 Combination Unlock (Subroutine) .............................. 50 Fast Register Stack ................................................... 45 Initializing PORTA .................................................... 103 Initializing PORTB .................................................... 105 Initializing PORTC ................................................... 108 Initializing PORTD ................................................... 110 Initializing PORTE .................................................... 113 Initializing PORTF .................................................... 116 Initializing PORTG ................................................... 119 Initializing PORTH ................................................... 121 Initializing PORTJ .................................................... 124 Programming Chip Select Signals ........................... 116 Saving STATUS, WREG and BSR Registers .......... 101 Table Read ................................................................ 75 Table Write ................................................................ 77 COMF .............................................................................. 232 Compare (CCP Module) .................................................. 144 Block Diagram ......................................................... 144 CCP Pin Configuration ............................................. 144 CCPR1H:CCPR1L Registers ................................... 144 Software Interrupt .................................................... 144 Special Event Trigger .................... 133, 139, 144, 200 Timer1 Mode Selection ............................................ 144 Configuration Address Map, Example ............................... 71 Configuration Bits ............................................................ 207 Table ........................................................................ 207 Context Saving During Interrupts ..................................... 101 CPFSEQ .......................................................................... 232 CPFSGT .......................................................................... 233 CPFSLT ........................................................................... 233 D Data Memory ..................................................................... 49 General Purpose Registers ....................................... 49 Special Function Registers ........................................ 49 Data Memory Map Program Bit Not Set .................................................. 51 Program Bit Set ......................................................... 52 DAW ................................................................................ 234 DC and AC Characteristics Graphs and Tables .............. 295 DCFSNZ .......................................................................... 235 DECF ............................................................................... 234 DECFSZ .......................................................................... 235 Development Support ...................................................... 259 Development Tool Version Requirements ....................... 305 Device Differences .......................................................... 303 Device Migrations ............................................................ 304 Direct Addressing .............................................................. 60 E Electrical Characteristics ................................................. 265 Errata ................................................................................... 7 External Wait Cycles ......................................................... 72 F Fast Register Stack ........................................................... 45 Firmware Instructions ...................................................... 215 G General Call Address Sequence ..................................... 162 General Call Address Support ......................................... 162 GOTO .............................................................................. 236 I I/O Mode .......................................................................... 119 I/O Ports .......................................................................... 103 I2C (SSP Module) ............................................................ 159 ACK Pulse .......................................................159, 160 Addressing .............................................................. 160 Block Diagram ......................................................... 159 Read/Write Bit Information (R/W Bit) ....................... 160 Reception ................................................................ 160 Serial Clock (RC3/SCK/SCL) .................................. 160 Slave Mode ............................................................. 159 Timing Diagram, Data ............................................. 287 Timing Diagram, START/STOP Bits ....................... 287 Transmission ........................................................... 160 I2C Master Mode Reception ............................................ 167 I2C Master Mode RESTART Condition ........................... 166 I2C Module Acknowledge Sequence Timing .............................. 170 Baud Rate Generator .............................................. 164 Block Diagram ................................................. 164 BRG Reset due to SDA Collision ............................ 174 BRG Timing ............................................................. 165 Bus Collision Acknowledge ................................................... 172 RESTART Condition ....................................... 175 RESTART Condition Timing (Case1) .............. 175 RESTART Condition Timing (Case2) .............. 175 START Condition ............................................ 173 START Condition Timing ........................173, 174 STOP Condition .............................................. 176 STOP Condition Timing (Case1) ..................... 176 STOP Condition Timing (Case2) ..................... 176 Transmit Timing .............................................. 172 Bus Collision Timing ................................................ 172 DS39541A-page 308 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 Clock Arbitration ...................................................... 171 Clock Arbitration Timing (Master Transmit) ............. 171 General Call Address Support ................................. 162 Master Mode 7-bit Reception Timing ....................... 169 Master Mode Operation ........................................... 164 Master Mode START Condition ............................... 165 Master Mode Transmission ..................................... 167 Master Mode Transmit Sequence ........................... 164 Multi-Master Mode ................................................... 172 Repeated START Condition Timing ........................ 166 STOP Condition Receive or Transmit Timing .......... 170 STOP Condition Timing ........................................... 170 Waveforms for 7-bit Reception ................................ 161 Waveforms for 7-bit Transmission ........................... 161 ICEPIC In-Circuit Emulator .............................................. 260 INCF ................................................................................ 236 INCFSZ ............................................................................ 237 In-Circuit Serial Programming (ICSP) .............................. 207 Indirect Addressing ............................................................ 60 FSR Register ............................................................. 59 INFSNZ ............................................................................ 237 Initialization Conditions for All Registers ............................ 34 Instruction Cycle ................................................................ 46 Instruction Flow/Pipelining ................................................. 47 Instruction Format ............................................................ 217 Instruction Set .................................................................. 215 ADDLW .................................................................... 221 ADDWF ................................................................... 221 ADDWFC ................................................................. 222 ANDLW .................................................................... 222 ANDWF ................................................................... 223 BC ............................................................................ 223 BCF ......................................................................... 224 BN ............................................................................ 224 BNC ......................................................................... 225 BNN ......................................................................... 225 BNOV ...................................................................... 226 BNZ ......................................................................... 226 BOV ......................................................................... 229 BRA ......................................................................... 227 BSF .......................................................................... 227 BTFSC ..................................................................... 228 BTFSS ..................................................................... 228 BTG ......................................................................... 229 BZ ............................................................................ 230 CALL ........................................................................ 230 CLRF ....................................................................... 231 CLRWDT ................................................................. 231 COMF ...................................................................... 232 CPFSEQ .................................................................. 232 CPFSGT .................................................................. 233 CPFSLT ................................................................... 233 DAW ........................................................................ 234 DCFSNZ .................................................................. 235 DECF ....................................................................... 234 DECFSZ .................................................................. 235 GOTO ...................................................................... 236 INCF ........................................................................ 236 INCFSZ .................................................................... 237 INFSNZ .................................................................... 237 IORLW ..................................................................... 238 IORWF ..................................................................... 238 LFSR ....................................................................... 239 MOVF ...................................................................... 239 MOVFF .................................................................... 240 MOVLB .................................................................... 240 MOVLW ................................................................... 241 MOVWF .................................................................. 241 MULLW ................................................................... 242 MULWF ................................................................... 242 NEGF ...................................................................... 243 NOP ........................................................................ 243 POP ......................................................................... 244 PUSH ...................................................................... 244 RCALL ..................................................................... 245 RESET .................................................................... 245 RETFIE ................................................................... 246 RETLW .................................................................... 246 RETURN ................................................................. 247 RLCF ....................................................................... 247 RLNCF .................................................................... 248 RRCF ...................................................................... 248 RRNCF .................................................................... 249 SETF ....................................................................... 249 SLEEP ..................................................................... 250 SUBFWB .........................................................250, 251 SUBLW ................................................................... 251 SUBWF ................................................................... 252 SUBWFB ................................................................. 253 SWAPF ................................................................... 254 TBLRD .................................................................... 255 TBLWT .................................................................... 256 TSTFSZ ................................................................... 257 XORLW ................................................................... 257 XORWF ................................................................... 258 Instruction Set, Summary ................................................ 218 INT Interrupt (RB0/INT). See Interrupt Sources INTCON Register RBIF Bit ................................................................... 105 Inter-Integrated Circuit. See I2C Interrupt Control Registers ................................................ 91 INTCON Register ...................................................... 91 INTCON2 Register .................................................... 92 INTCON3 Register .................................................... 93 IPR Registers ............................................................ 99 PIE Registers ............................................................ 97 PIR Registers ............................................................ 95 RCON Register ......................................................... 94 Interrupt Sources .......................................................89, 207 A/D Conversion Complete ....................................... 197 Capture Complete (CCP) ........................................ 143 Compare Complete (CCP) ...................................... 144 Interrupt-on-Change (RB7:RB4) ............................. 105 RB0/INT Pin, External ............................................. 101 SSP Receive/Transmit Complete ............................ 149 TMR0 Overflow ....................................................... 129 TMR1 Overflow ...............................................130, 133 TMR2 to PR2 Match ................................................ 136 TMR2 to PR2 Match (PWM) ...........................135, 146 TMR3 Overflow ...............................................137, 139 USART Receive/Transmit Complete ....................... 177 Interrupts, Enable Bits CCP1 Enable (CCP1IE Bit) ..................................... 143 Interrupts, Flag Bits A/D Converter Flag (ADIF Bit) ................................. 195 CCP1 Flag (CCP1IF Bit) ........................ 142, 143, 144 Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) ................................................ 105 IORLW ............................................................................. 238 IORWF ............................................................................ 238 2001 Microchip Technology Inc. Advance Information DS39541A-page 309 PIC18C601/801 K KEELOQ Evaluation and Programming Tools ................... 262 P Packaging ........................................................................ 297 Phase Lock Loop Block Diagram ........................................................... 23 Time-out .................................................................... 30 PICDEM 1 Low Cost PICmicro Demonstration Board .............................................. 261 PICDEM 17 Demonstration Board .................................. 262 PICDEM 2 Low Cost PIC16CXX Demonstration Board .............................................. 261 PICDEM 3 Low Cost PIC16CXXX Demonstration Board .............................................. 262 PICSTART Plus Entry Level Development Programmer ...................................... 261 Pin Functions AVDD .......................................................................... 20 AVSS .......................................................................... 20 MCLR/VPP ................................................................. 12 OSC1/CLKI ................................................................ 12 OSC2/CLKO .............................................................. 12 RA0/AN0 ................................................................... 13 RA1/AN1 ................................................................... 13 RA2/AN2/VREF- ......................................................... 13 RA3/AN3/VREF+ ........................................................ 13 RA4/T0CKI ................................................................ 13 RA5/AN4/SS/LVDIN .................................................. 13 RB0/INT0 ................................................................... 14 RB1/INT1 ................................................................... 14 RB2/INT2 ................................................................... 14 RB3/INT3 ................................................................... 14 RB4 ........................................................................... 14 RB5 ........................................................................... 14 RB6 ........................................................................... 14 RB7 ........................................................................... 14 RC0/T1OSO/T1CKI ................................................... 15 RC1/T1OSI ................................................................ 15 RC2/CCP1 ................................................................. 15 RC3/SCK/SCL ........................................................... 15 RC4/SDI/SDA ............................................................ 15 RC5/SDO .................................................................. 15 RC6/TX/CK ................................................................ 15 RC7/RX/DT ............................................................... 15 RD0/AD0 ................................................................... 16 RD0/PSP0 ................................................................. 16 RD1/AD1 ................................................................... 16 RD2/AD2 ................................................................... 16 RD3/AD3 ................................................................... 16 RD4/AD4 ................................................................... 16 RD5/AD5 ................................................................... 16 RD6/AD6 ................................................................... 16 RD7/AD7 ................................................................... 16 RE0/ALE .................................................................... 17 RE1/OE ..................................................................... 17 RE2/CS ........................................................ 17, 18, 19 RE2/WRL .................................................................. 17 RE3/WRH .................................................................. 17 RE4 ........................................................................... 17 RE5 ........................................................................... 17 RE6 ........................................................................... 17 RE7/CCP2 ................................................................. 17 RF0/AN5 .................................................................... 18 RF1/AN6 .................................................................... 18 RF2/AN7 .................................................................... 18 RF3/AN8 .................................................................... 18 RF4/AN9 .................................................................... 18 L LFSR ................................................................................ 239 Loading the SSPBUF (SSPSR) Registers ....................... 154 Low Voltage Detect .......................................................... 203 Block Diagram ......................................................... 203 LVDCON Register ................................................... 204 LVD. See Low Voltage Detect. M MEMCOM. See Memory Control Register Memory .............................................................................. 39 Memory Control Register (MEMCOM) ............................... 63 Memory Organization ........................................................ 39 Data Memory ............................................................. 49 Program Memory ....................................................... 39 Migrating from other PICmicro Devices ........................... 304 MOVF .............................................................................. 239 MOVFF ............................................................................ 240 MOVLB ............................................................................ 240 MOVLW ........................................................................... 241 MOVWF ........................................................................... 241 MPLAB C17 and MPLAB C18 C Compilers .................... 259 MPLAB ICD In-Circuit Debugger ..................................... 261 MPLAB ICE High Performance Universal In-Circuit Emulator with MPLAB IDE ....................... 260 MPLAB Integrated Development Environment Software ............................................. 259 MPLINK Object Linker/MPLIB Object Librarian ............... 260 MULLW ............................................................................ 242 Multi-Master Mode ........................................................... 172 Multiplication Algorithm 16 x 16 Signed ........................................................... 86 16 x 16 Unsigned ....................................................... 86 Multiply Examples 16 x 16 Signed Routine ............................................. 87 16 x 16 Unsigned Routine ......................................... 86 8 x 8 Signed Routine ................................................. 86 8 x 8 Unsigned Routine ............................................. 86 MULWF ............................................................................ 242 N NEGF ............................................................................... 243 NOP ................................................................................. 243 O On-Chip Reset Circuit ........................................................ 29 OPTION_REG Register ..................................................... 62 PS2:PS0 Bits ........................................................... 129 PSA Bit .................................................................... 129 T0CS Bit .................................................................. 129 T0SE Bit ................................................................... 129 OSCCON Register ............................................................. 25 Oscillator Configuration ................................................... 207 Oscillator Configurations .................................................... 21 HS .............................................................................. 21 LP .............................................................................. 21 RC ....................................................................... 21, 22 Oscillator, Timer1 ............................................130, 133, 137 Oscillator, Timer3 ............................................................. 139 Oscillator, WDT ................................................................ 210 DS39541A-page 310 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 RF5/AN10 .................................................................. 18 RF6/AN11 .................................................................. 18 RF7 ............................................................................ 18 RG0/CANTX1 ............................................................ 19 RG1/CANTX2 ............................................................ 19 RG2/CANRX .............................................................. 19 RG3 ........................................................................... 19 RG4 ........................................................................... 19 RH1/A17 .................................................................... 19 RH2/A18 .................................................................... 19 RH3/A19 .................................................................... 19 RH4/AN12 ................................................................. 19 RH5/AN13 ................................................................. 19 RH6/AN14 ................................................................. 19 RH7/AN15 ................................................................. 19 RJ0/AD8 .................................................................... 20 RJ1/AD9 .................................................................... 20 RJ2/AD10 .................................................................. 20 RJ3/AD11 .................................................................. 20 RJ4/AD12 .................................................................. 20 RJ5/AD13 .................................................................. 20 RJ6/AD14 .................................................................. 20 RJ7/AD15 .................................................................. 20 VDD ............................................................................ 20 VSS ............................................................................ 20 POP ................................................................................. 244 POR. See Power-on Reset PORTA Associated Registers ............................................... 104 Block Diagram RA3:RA0 and RA5 Pins ................................... 103 RA4/T0CKI Pin ................................................ 104 Functions ................................................................. 104 Initialization .............................................................. 103 PORTA Register ...................................................... 103 TRISA Register ........................................................ 103 PORTB Associated Registers ............................................... 107 Block Diagram RB3 Pin ........................................................... 106 RB3:RB0 Port Pins .......................................... 106 RB7:RB4 Port Pins .......................................... 105 Functions ................................................................. 107 Initialization .............................................................. 105 PORTB Register ...................................................... 105 RB0/INT Pin, External ............................................. 101 RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) ....... 105 TRISB Register ........................................................ 105 PORTC Associated Registers ............................................... 109 Block Diagram ......................................................... 108 Functions ................................................................. 109 Initialization .............................................................. 108 PORTC Register ...................................................... 108 RC3/SCK/SCL Pin ................................................... 160 RC7/RX/DT Pin ....................................................... 179 TRISC Register .............................................. 108, 177 PORTD Associated Registers ............................................... 112 Block Diagram I/O Mode .......................................................... 110 System Bus Mode ........................................... 111 Functions ................................................................. 112 Initialization .............................................................. 110 PORTD Register ...................................................... 110 TRISD Register ....................................................... 110 PORTE Associated Registers .............................................. 115 Block Diagram I/O Mode ......................................................... 113 System Bus Mode ........................................... 114 Functions ................................................................. 115 Initialization ............................................................. 113 PORTE Register ..................................................... 113 TRISE Register ....................................................... 113 PORTF Associated Registers .............................................. 118 Block Diagram RF2:RF0 Pins .................................................. 116 RF5:RF3 Pins .................................................. 117 RF7:RF6 Pins .................................................. 117 Functions ................................................................. 118 Initialization ............................................................. 116 PORTF Register ...................................................... 116 TRISF ...................................................................... 116 PORTG ............................................................................ 119 Associated Registers .............................................. 120 Block Diagram System Bus Mode ........................................... 120 Functions ................................................................. 120 Initialization ............................................................. 119 PORTG Register ..................................................... 119 TRISG ..................................................................... 119 PORTH Associated Registers .............................................. 123 Block Diagram .................................................121, 122 Functions ................................................................. 123 Initialization ............................................................. 121 PORTH Register ..................................................... 121 TRISH ..................................................................... 121 PORTJ Associated Registers .............................................. 126 Block Diagram I/O Mode ......................................................... 124 System Bus Mode ........................................... 125 Functions ................................................................. 126 Initialization ............................................................. 124 PORTJ Register ...................................................... 124 TRISJ ...................................................................... 124 Postscaler, WDT Assignment (PSA Bit) .............................................. 129 Rate Select (PS2:PS0 Bits) ..................................... 129 Switching Between Timer0 and WDT ..................... 129 Power-down Mode. See SLEEP Power-on Reset (POR) .............................................30, 207 Oscillator Start-up Timer (OST) ........................30, 207 Power-up Timer (PWRT) ...................................30, 207 Time-out Sequence ................................................... 30 Time-out Sequence on Power-up .......................32, 33 Timing Diagram ....................................................... 280 Prescaler, Capture .......................................................... 143 Prescaler, Timer0 ............................................................ 129 Assignment (PSA Bit) .............................................. 129 Rate Select (PS2:PS0 Bits) ..................................... 129 Switching Between Timer0 and WDT ..................... 129 Prescaler, Timer1 ............................................................ 131 Prescaler, Timer2 ............................................................ 146 PRO MATE II Universal Device Programmer .................. 261 Product Identification System .......................................... 317 2001 Microchip Technology Inc. Advance Information DS39541A-page 311 PIC18C601/801 Program Counter PCL Register ............................................................. 46 PCLATH Register ...................................................... 46 Program Memory ............................................................... 39 Boot Loader ............................................................... 43 Memory Map, PIC18C601 Program Bit Not Set ........................................... 40 Program Bit Set ................................................. 41 Memory Map, PIC18C801 Program Bit Not Set ........................................... 40 Program Bit Set ................................................. 42 Program Memory Map PIC18C601 ................................................................ 40 Program Bit Set ................................................. 41 PIC18C801 ................................................................ 40 Program Bit Set ................................................. 42 Programming, Device Instructions ................................... 215 PUSH ............................................................................... 244 PWM (CCP Module) ........................................................ 146 Block Diagram ......................................................... 146 CCPR1H:CCPR1L Registers ................................... 146 Duty Cycle ............................................................... 146 Example Frequencies/Resolutions .......................... 147 Output Diagram ....................................................... 146 Period ...................................................................... 146 Registers Associated with PWM .............................. 147 Setup for PWM Operation ........................................ 147 TMR2 to PR2 Match ....................................... 135, 146 RCSTA (Receive Status and Control) ..................... 178 SSPCON1 (SSP Control 1) ..................................... 151 SSPCON2 (SSP Control 2) ...................................... 152 SSPSTAT (SSP Status) .......................................... 150 STATUS .................................................................... 61 STKPTR (Stack Pointer) ........................................... 44 T0CON (Timer0 Control) ......................................... 127 T1CON (Timer1 Control) ......................................... 130 T2CON (Timer2 Control) ......................................... 135 T3CON (Timer3 Control) ......................................... 137 TXSTA (Transmit Status and Control) ..................... 177 WDTCON (Watchdog Timer Control) ...................... 210 RESET ............................................................. 29, 207, 245 Timing Diagram ....................................................... 280 RETFIE ............................................................................ 246 RETLW ............................................................................ 246 RETURN ......................................................................... 247 Revision History .............................................................. 303 RH3:RH0 Pins (I/O Mode) ............................................... 121 RH3:RH0 Pins (System Bus Mode) ................................ 122 RH7:RH4 Pins ................................................................. 121 RLCF ............................................................................... 247 RLNCF ............................................................................ 248 RRCF .............................................................................. 248 RRNCF ............................................................................ 249 S Sales and Support ........................................................... 317 SCI. See USART SCK ................................................................................. 153 SDI .................................................................................. 153 SDO ................................................................................. 153 Serial Clock, SCK ............................................................ 153 Serial Communication Interface. See USART Serial Data In, SDI ........................................................... 153 Serial Data Out, SDO ...................................................... 153 Serial Peripheral Interface. See SPI SETF ............................................................................... 249 Slave Select Synchronization .......................................... 156 Slave Select, SS .............................................................. 153 SLEEP ............................................................ 207, 212, 250 Software Simulator (MPLAB SIM) ................................... 260 Special Event Trigger. See Compare Special Features of the CPU ........................................... 207 Special Function Register Map ......................................... 53 Special Function Registers ................................................ 49 SPI Associated Registers ............................................... 158 Master Mode ........................................................... 155 Serial Clock ............................................................. 153 Serial Data In ........................................................... 153 Serial Data Out ........................................................ 153 Slave Select ............................................................ 153 SPI Clock ................................................................. 155 SPI Mode ................................................................. 153 SPI Module Slave Mode ............................................................. 156 Slave Select Synchronization .................................. 156 Slave Synch Timing ................................................. 156 Slave Timing with CKE = 0 ...................................... 157 Slave Timing with CKE = 1 ...................................... 157 SS .................................................................................... 153 Q Q Clock ............................................................................ 146 R RAM. See Data Memory RCALL ............................................................................. 245 RCSTA Register SPEN Bit .................................................................. 177 Reader Response ............................................................ 316 Register File ....................................................................... 49 Register File Summary ...................................................... 54 Registers ADCON0 (A/D Control 0) .......................................... 193 ADCON1 (A/D Control 1) ......................................... 194 CCP1CON and CCP2CON (CCP Control) .............. 141 CONFIG1H (Configuration Register 1 High) ............ 208 CONFIG2H (Configuration Register 2 High) ............ 209 CONFIG2L (Configuration Register 2 Low) ............. 208 CONFIG4L (Configuration Register 4 Low) ............. 209 CSEL2 (Chip Select 2) ............................................... 70 CSELIO (Chip Select I/O) .......................................... 70 INTCON (Interrupt Control) ........................................ 91 INTCON2 (Interrupt Control 2) ................................... 92 INTCON3 (Interrupt Control 3) ................................... 93 IPR (Interrupt Priority) ................................................ 99 LVDCON (LVD Control) ........................................... 204 MEMCON (Memory Control) ..................................... 63 OSCCON (Oscillator Control) .................................... 25 PIE (Peripheral Interrupt Enable) ............................... 97 PIR (Peripheral Interrupt Request) ............................ 95 PSPCON (PSP Control) ............................................ 50 RCON (Register Control) ........................................... 94 RCON (RESET Control) ..................................... 31, 62 DS39541A-page 312 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 SSP .................................................................................. 149 Block Diagram SPI Mode ......................................................... 153 Block Diagram (SPI Mode) ...................................... 153 I2C Mode. See I2C SPI Mode ................................................................. 153 SPI Mode. See SPI SSPBUF .................................................................. 155 SSPCON1 ............................................................... 151 SSPCON2 ............................................................... 152 SSPSR .................................................................... 155 SSPSTAT ................................................................ 150 TMR2 Output for Clock Shift ........................... 135, 136 SSP Module SPI Master Mode ..................................................... 155 SPI Slave Mode ....................................................... 156 SSPCON1 Register ......................................................... 151 SSPCON2 Register ......................................................... 152 SSPOV ............................................................................ 167 SSPSTAT Register .......................................................... 150 R/W Bit .................................................................... 160 SUBFWB ................................................................ 250, 251 SUBLW ............................................................................ 251 SUBWF ............................................................................ 252 SUBWFB ......................................................................... 253 SWAPF ............................................................................ 254 Synchronous Serial Port. See SSP Prescaler. See Prescaler, Timer1 Special Event Trigger (CCP) ...........................133, 144 T1CON Register ...................................................... 130 Timing Diagram ....................................................... 281 TMR1H Register ..................................................... 130 TMR1L Register ...................................................... 130 TMR3L Register ...................................................... 137 Timer2 Associated Registers .............................................. 136 Block Diagram ......................................................... 136 Postscaler. See Postscaler, Timer2 PR2 Register ...................................................135, 146 Prescaler. See Prescaler, Timer2 SSP Clock Shift ...............................................135, 136 T2CON Register ...................................................... 135 TMR2 Register ........................................................ 135 TMR2 to PR2 Match Interrupt ................ 135, 136, 146 Timer3 ............................................................................. 137 Associated Registers .............................................. 139 Block Diagram ......................................................... 138 16-bit R/W Mode ............................................. 138 Oscillator .........................................................137, 139 Overflow Interrupt ............................................137, 139 Special Event Trigger (CCP) ................................... 139 T3CON Register ...................................................... 137 TMR3H Register ..................................................... 137 Timing Diagrams Acknowledge Sequence Timing .............................. 170 Baud Rate Generator with Clock Arbitration ........... 165 BRG Reset Due to SDA Collision ........................... 174 Bus Collision START Condition Timing ................................ 173 Bus Collision During a RESTART Condition (Case 1) .................................................. 175 Bus Collision During a RESTART Condition (Case 2) .................................................. 175 Bus Collision During a START Condition (SCL = 0) ................................................. 174 Bus Collision During a STOP Condition .................. 176 Bus Collision for Transmit and Acknowledge .......... 172 I2C Bus Data ........................................................... 289 I2C Master Mode First START Bit Timing ............... 165 I2C Master Mode Reception Timing ........................ 169 I2C Master Mode Transmission Timing ................... 168 Master Mode Transmit Clock Arbitration ................. 171 Repeated START Condition .................................... 166 Slave Synchronization ............................................. 156 Slow Rise Time ......................................................... 33 SPI Mode Timing (Master Mode) SPI Mode Master Mode Timing Diagram ......................... 155 SPI Mode Timing (Slave Mode with CKE = 0) ........ 157 SPI Mode Timing (Slave Mode with CKE = 1) ........ 157 STOP Condition Receive or Transmit ..................... 170 Time-out Sequence on Power-up ............................. 32 USART Asynchronous Master Transmission .......... 184 USART Asynchronous Reception ........................... 186 USART Synchronous Reception ............................. 189 USART Synchronous Transmission ........................ 188 Wake-up from SLEEP via Interrupt ......................... 213 T Table Pointer Register ....................................................... 74 Table Read ........................................................................ 75 Table Read/Write Control Registers .................................. 74 Table Write ........................................................................ 77 16-bit External 16-bit Word Write Mode ..................................... 81 Byte Select Mode .............................................. 82 Byte Write Mode ................................................ 80 8-bit External ............................................................. 78 Table Writes Long Writes ............................................................... 83 TBLRD ............................................................................. 255 TBLWT ............................................................................. 256 Timer0 .............................................................................. 127 Associated Registers ............................................... 129 Block Diagram 16-bit Mode ...................................................... 128 8-bit Mode ........................................................ 128 Clock Source Edge Select (T0SE Bit) ..................... 129 Clock Source Select (T0CS Bit) .............................. 129 Interrupt ................................................................... 101 Overflow Interrupt .................................................... 129 Prescaler. See Prescaler, Timer0 T0CON Register ...................................................... 127 Timing Diagram ....................................................... 281 Timer1 .............................................................................. 130 Associated Registers ............................................... 134 Block Diagram ......................................................... 131 16-bit R/W Mode .............................................. 132 Oscillator ......................................................... 130, 133 Overflow Interrupt ........................................... 130, 133 2001 Microchip Technology Inc. Advance Information DS39541A-page 313 PIC18C601/801 Timing Diagrams and Specifications ............................... 275 A/D Conversion ........................................................ 293 Capture/Compare/PWM (CCP) ............................... 282 CLKOUT and I/O ..................................................... 276 External Clock .......................................................... 275 I2C Bus Data ............................................................ 287 I2C Bus START/STOP Bits ...................................... 287 Oscillator Start-up Timer (OST) ............................... 280 Power-up Timer (PWRT) ......................................... 280 RESET ..................................................................... 280 Timer0 and Timer1 .................................................. 281 USART Synchronous Receive (Master/Slave) ......................................... 291 USART Synchronous Transmission (Master/Slave) ......................................... 291 Watchdog Timer (WDT) ........................................... 280 TRISE Register ................................................................ 113 TSTFSZ ........................................................................... 257 Two-Word Instructions ....................................................... 48 TXSTA Register ............................................................... 177 BRGH Bit ................................................................. 179 W Wake-up from SLEEP .............................................207, 212 Timing Diagram ....................................................... 213 Watchdog Timer (WDT) ..........................................207, 210 Associated Registers ............................................... 211 Block Diagram ......................................................... 211 Postscaler. See Postscaler, WDT Programming Considerations .................................. 210 RC Oscillator ........................................................... 210 Time-out Period ....................................................... 210 Timing Diagram ....................................................... 280 WDTCON Register .................................................. 210 Waveform for General Call Address Sequence .............. 162 WCOL ............................................................. 165, 167, 170 WCOL Status Flag .......................................................... 165 Worldwide Sales and Service .......................................... 318 WWW, On-Line Support ..............................................7, 315 X XORLW ........................................................................... 257 XORWF ........................................................................... 258 U Universal Synchronous Asynchronous Receiver Transmitter. See USART USART ............................................................................. 177 Asynchronous Mode ................................................ 183 Master Transmission ....................................... 184 Receive Block Diagram ................................... 185 Reception ........................................................ 186 Registers Associated with Reception .............. 186 Registers Associated with Transmission ......... 184 Transmit Block Diagram .................................. 183 Baud Rate Generator (BRG) ................................... 179 Baud Rate Error, Calculating ........................... 179 Baud Rate Formula ......................................... 179 High Baud Rate Select (BRGH Bit) ................. 179 Sampling .......................................................... 179 Serial Port Enable (SPEN Bit) ................................. 177 Synchronous Master Mode ...................................... 187 Reception ........................................................ 189 Registers Associated with Reception .............. 189 Registers Associated with Transmission ......... 187 Timing Diagram, Synchronous Receive ..................... 291 Timing Diagram, Synchronous Transmission ............. 291 Transmission ................................................... 188 Synchronous Slave Mode ........................................ 190 Registers Associated with Reception .............. 191 Registers Associated with Transmission ......... 190 DS39541A-page 314 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site. Systems Information and Upgrade Hot Line The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. 001024 Connecting to the Microchip Internet Web Site The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products * Conferences for products, Development Systems, technical information and more * Listing of seminars and events Trademarks: The Microchip name, logo, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, KEELOQ, SEEVAL, MPLAB and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Total Endurance, ICSP, In-Circuit Serial Programming, FilterLab, MXDEV, microID, FlexROM, fuzzyLAB, MPASM, MPLINK, MPLIB, PICDEM, ICEPIC and Migratable Memory are trademarks and SQTP is a service mark of Microchip in the U.S.A. All other trademarks mentioned herein are the property of their respective companies. 2001 Microchip Technology Inc. Advance Information DS39541A-page 315 PIC18C601/801 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: RE: Technical Publications Manager Reader Response Total Pages Sent From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: PIC18C601/801 Questions: 1. What are the best features of this document? Y N Literature Number: DS39541A FAX: (______) _________ - _________ 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this data sheet easy to follow? If not, why? 4. What additions to the data sheet do you think would enhance the structure and subject? 5. What deletions from the data sheet could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? DS39541A-page 316 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples: a) b) PIC18LC601 - I/L = Industrial temp., PLCC package, Extended VDD limits, 16-bit data bus. PIC18LC801 - E/PT = Extended temp., TQFP package, Extended VDD limits, 16-bit data bus. Device PIC18C601/801(1), PIC18C601/801T(2): VDD range, 4.2V to 5.5V PIC18LC601/801(1), PIC18LC601/801T(2) VDD range, 2.5V to 5.5V Temperature Range I E = = -40C to +70C (Industrial) -40C to +125C (Extended) Package PT L = = TQFP PLCC Note 1: C = LC = 2: T = Standard Voltage Range Wide Voltage Range In tape and reel (both PLCC and TQFP packages) Pattern QTP, SQTP, ROM Code (factory specified) or Special Requirements. Blank for OTP and Windowed devices. SALES AND SUPPORT Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2001 Microchip Technology Inc. Advance Information DS39541A-page 317 PIC18C601/801 NOTES: DS39541A-page 318 Advance Information 2001 Microchip Technology Inc. PIC18C601/801 NOTES: 2001 Microchip Technology Inc. Advance Information DS39541A-page 319 WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com ASIA/PACIFIC China - Beijing Microchip Technology Beijing Office Unit 915 New China Hong Kong Manhattan Bldg. No. 6 Chaoyangmen Beidajie Beijing, 100027, No. China Tel: 86-10-85282100 Fax: 86-10-85282104 ASIA/PACIFIC (continued) Singapore Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-334-8870 Fax: 65-334-8850 Rocky Mountain 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7966 Fax: 480-792-7456 Taiwan Microchip Technology Taiwan 11F-3, No. 207 Tung Hua North Road Taipei, 105, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139 China - Shanghai Microchip Technology Shanghai Office Room 701, Bldg. B Far East International Plaza No. 317 Xian Xia Road Shanghai, 200051 Tel: 86-21-6275-5700 Fax: 86-21-6275-5060 Atlanta 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307 EUROPE Denmark Microchip Technology Denmark ApS Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45 4420 9895 Fax: 45 4420 9910 Boston 2 Lan Drive, Suite 120 Westford, MA 01886 Tel: 978-692-3848 Fax: 978-692-3821 Hong Kong Microchip Asia Pacific RM 2101, Tower 2, Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Chicago 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075 India Microchip Technology Inc. India Liaison Office Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O'Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-2290061 Fax: 91-80-2290062 France Arizona Microchip Technology SARL Parc d'Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Dallas 4570 Westgrove Drive, Suite 160 Addison, TX 75001 Tel: 972-818-7423 Fax: 972-818-2924 Dayton Two Prestige Place, Suite 130 Miamisburg, OH 45342 Tel: 937-291-1654 Fax: 937-291-9175 Germany Arizona Microchip Technology GmbH Gustav-Heinemann Ring 125 D-81739 Munich, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44 Japan Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Detroit Tri-Atria Office Building 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260 Italy Arizona Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883 Korea Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea Tel: 82-2-554-7200 Fax: 82-2-558-5934 Los Angeles 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 949-263-1888 Fax: 949-263-1338 United Kingdom Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820 10/01/00 New York 150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 631-273-5305 Fax: 631-273-5335 San Jose Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955 Toronto 6285 Northam Drive, Suite 108 Mississauga, Ontario L4V 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509 Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified. All rights reserved. (c) 2001 Microchip Technology Incorporated. Printed in the USA. 1/01 Printed on recycled paper. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. DS39541A-page 320 Advance Information 2001 Microchip Technology Inc. |
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